公开(公告)号：US11721404B2

公开(公告)日：2023-08-08

申请号：US17484777

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/30 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C16/349 ,  G11C16/12 ,  G11C2211/5641

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

公开(公告)号：US11720286B2

公开(公告)日：2023-08-08

申请号：US17516009

申请日：2021-11-01

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Kishore Kumar Muchherla ,  Shane Nowell ,  Peter Feeley ,  Qisong Lin

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.

公开(公告)号：US11709727B2

公开(公告)日：2023-07-25

申请号：US17216901

申请日：2021-03-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Sampath K. Ratnam ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0727 ,  G06F11/0751

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.

公开(公告)号：US20230205438A1

公开(公告)日：2023-06-29

申请号：US18114967

申请日：2023-02-27

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Peter Feeley ,  Sampath K. Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Karl D. Schuh ,  Jiangang Wu

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/26

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.

公开(公告)号：US11620074B2

公开(公告)日：2023-04-04

申请号：US17203474

申请日：2021-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Devin M. Batutis ,  Xiangang Luo ,  Mustafa N. Kaynak ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Sampath Ratnam ,  Shane Nowell

IPC: G06F3/00 ,  G06F3/06

Abstract: A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.

公开(公告)号：US11587639B2

公开(公告)日：2023-02-21

申请号：US17198755

申请日：2021-03-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Xiangang Luo ,  Peter Feeley ,  Devin M. Batutis ,  Jiangang Wu ,  Sampath K Ratnam ,  Shane Nowell ,  Karl D. Schuh

IPC: G11C29/00 ,  G11C29/50 ,  G06F12/02 ,  G11C16/26 ,  G11C29/02 ,  G11C7/10

Abstract: A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped.

公开(公告)号：US20230017591A1

公开(公告)日：2023-01-19

申请号：US17949977

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Jiangang Wu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Peter Feeley ,  Karl D. Schuh

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/04

Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.

公开(公告)号：US11544188B2

公开(公告)日：2023-01-03

申请号：US17196934

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： Yun Li ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0891

Abstract: Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.

公开(公告)号：US20220334721A1

公开(公告)日：2022-10-20

申请号：US17846378

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Peter Feeley ,  Larry J. Koudele ,  Shane Nowell ,  Steven Michael Kientz

IPC: G06F3/06

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising assigning a plurality of data streams to a block family comprising a plurality of blocks of a memory device; responsive to programming a first block associated with a first data stream of the plurality of data streams, associating the first block with the block family; and responsive to programming a second block associated with a second data stream of the plurality of data streams, associating the second block with the block family.

公开(公告)号：US20220318086A1

公开(公告)日：2022-10-06

申请号：US17216901

申请日：2021-03-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Sampath K. Ratnam ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F11/07

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.