公开(公告)号：US20170154656A1

公开(公告)日：2017-06-01

申请号：US14997575

申请日：2016-01-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G11C7/00 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C7/00 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G11C5/005 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/345 ,  G11C29/42 ,  G11C29/52

Abstract: A data programming method and a memory storage device are provided. The method includes: programming a plurality of first type physical units in a rewritable non-volatile memory module to store first data; encoding the first data to generate encoded data; receiving second data; and programming at least one of a plurality of second type physical units in the rewritable non-volatile memory module corresponding to the first type physical units to store at least a part of the second data after the first data is encoded. Therefore, the correcting ability for correcting errors in pair physical units in multi-channel programming procedure may be improved.

公开(公告)号：US09619380B2

公开(公告)日：2017-04-11

申请号：US14038780

申请日：2013-09-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: A data writing method for a memory storage apparatus having a first buffer memory, a second buffer memory and a rewritable non-volatile memory module is provided, and the transmission bandwidth of the first buffer memory is larger than the transmission bandwidth of the second buffer memory. The method includes: receiving a write command and first data thereof; determining whether the first data belongs to the successive big data; if the first data belongs to the successive big data, temporarily storing the first data into a first data buffer area of the first buffer memory, writing the first write data from the first data buffer area to the rewritable non-volatile memory module; and if the first data does not belongs to the successive big data, temporarily storing the first data into a second data buffer area of the second buffer memory.

公开(公告)号：US20170038977A1

公开(公告)日：2017-02-09

申请号：US14872154

申请日：2015-10-01

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: A valid data merging method, a memory controller and a memory storage apparatus are provided. The method includes: selecting a first physical erasing unit, and loading a first logical address-physical address mapping table according to a physical address-logical address mapping table. The method also includes: updating the first logical address-physical address mapping table according to the physical address-logical address mapping table, and identifying valid data in the first physical erasing unit according to the physical address-logical address mapping table and the first logical address-physical address mapping table. The method further includes: storing the first logical address-physical address mapping table, copying the valid data to a second physical erasing unit, and performing an erasing operation for the first physical erasing unit.

Abstract translation: 提供有效的数据合并方法，存储器控制器和存储器存储装置。 该方法包括：选择第一物理擦除单元，并根据物理地址 - 逻辑地址映射表加载第一逻辑地址 - 物理地址映射表。 该方法还包括：根据物理地址 - 逻辑地址映射表更新第一逻辑地址 - 物理地址映射表，并根据物理地址 - 逻辑地址映射表和第一逻辑地址映射表识别第一物理擦除单元中的有效数据 地址 - 物理地址映射表。 该方法还包括：存储第一逻辑地址 - 物理地址映射表，将有效数据复制到第二物理擦除单元，以及对第一物理擦除单元执行擦除操作。

公开(公告)号：US20160314040A1

公开(公告)日：2016-10-27

申请号：US14736284

申请日：2015-06-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh ,  Chang-Guang Lin

IPC: G06F11/10 ,  H03M13/29 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1012 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/09 ,  H03M13/2906

Abstract: A data accessing method for a memory storage apparatus is provided. The method includes using a first check code circuit to generate a first check code corresponding to a first data stream and generating a first data set based on the first data stream and the first check code. The method also includes using a second check code circuit to obtain the first data stream and the first check code from the first data set and check the first data stream according to the first check code. The method still includes using a third check code circuit to generate a second check code according to the checked first data stream and generating a data frame based on the checked first data stream and the second check code and thereby programming the data frame into a physical programming unit.

Abstract translation: 提供了一种用于存储器存储装置的数据存取方法。 该方法包括使用第一校验码电路来生成与第一数据流相对应的第一校验码，并且基于第一数据流和第一校验码产生第一数据集。 该方法还包括使用第二校验码电路从第一数据集获得第一数据流和第一校验码，并根据第一校验码检查第一数据流。 该方法还包括使用第三检验码电路根据所检查的第一数据流生成第二检验码，并且基于所检查的第一数据流和第二检验码产生数据帧，从而将数据帧编程为物理编程 单元。

公开(公告)号：US09436547B2

公开(公告)日：2016-09-06

申请号：US14492081

申请日：2014-09-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F11/1048 ,  G06F11/1004 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G06F12/0246

Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes: generating a parity according to first data. The method also includes: when programming the first data into first physical programming unit, programming at least one mark into redundancy bit area of the first physical programming unit. The method further includes: programming the parity into at least one second physical programming unit arranged after the first physical programming unit, and the at least one mark indicates that the parity is programmed into the at least one second physical programming unit.

Abstract translation: 提供数据存储方法，存储器控制电路单元和存储器存储装置。 该方法包括：根据第一数据产生奇偶校验。 该方法还包括：当将第一数据编程到第一物理编程单元中时，将至少一个标记编程到第一物理编程单元的冗余位区域中。 该方法还包括：将奇偶校验编程到布置在第一物理编程单元之后的至少一个第二物理编程单元中，并且至少一个标记指示奇偶校验被编程到至少一个第二物理编程单元中。

公开(公告)号：US09268688B2

公开(公告)日：2016-02-23

申请号：US14583107

申请日：2014-12-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G06F11/10

CPC classification number: G06F12/0246 ,  G06F11/1068 ,  G06F2212/7201 ,  G06F2212/7207

Abstract: A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping a plurality of physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring a plurality of logical units for mapping a part of the physical units. The method further includes receiving at least two pieces of update data, which are corresponding to different logical pages of the logical units. The method further includes getting a physical unit from the physical units. The method further includes writing the at least two pieces of update data into the same one physical page of the gotten physical unit. Accordingly, the use efficiency of the physical units could be improved.

公开(公告)号：US20160034343A1

公开(公告)日：2016-02-04

申请号：US14492081

申请日：2014-09-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/1004 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G06F12/0246

Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes: generating a parity according to first data. The method also includes: when programming the first data into first physical programming unit, programming at least one mark into redundancy bit area of the first physical programming unit. The method further includes: programming the parity into at least one second physical programming unit arranged after the first physical programming unit, and the at least one mark indicates that the parity is programmed into the at least one second physical programming unit.

Abstract translation: 提供数据存储方法，存储器控制电路单元和存储器存储装置。 该方法包括：根据第一数据产生奇偶校验。 该方法还包括：当将第一数据编程到第一物理编程单元中时，将至少一个标记编程到第一物理编程单元的冗余位区域中。 该方法还包括：将奇偶校验编程到布置在第一物理编程单元之后的至少一个第二物理编程单元中，并且至少一个标记指示奇偶校验被编程到至少一个第二物理编程单元中。

公开(公告)号：US20160011930A1

公开(公告)日：2016-01-14

申请号：US14490684

申请日：2014-09-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/076 ,  G11C16/3418 ,  G11C16/349

Abstract: A method for preventing read-disturb errors, a memory storage apparatus and a memory control circuit unit are provided. The method includes counting an operation numerical value when receiving an operation command from the host system, wherein a first physical erasing unit is selected for executing the operation command. The method also includes selecting a second physical erasing unit and reading data from the second erasing unit. The method further includes determining whether a data error occurs at the second physical erasing unit according to the data read from the second physical erasing unit, and if the data error occurs, selecting a third physical erasing unit, correcting the data read from the second physical erasing unit to generate corrected data and writing the corrected data into the third physical erasing unit.

Abstract translation: 提供了一种用于防止读干扰错误的方法，存储器存储装置和存储器控制电路单元。 该方法包括当从主机系统接收到操作命令时对操作数值进行计数，其中选择第一物理擦除单元来执行操作命令。 该方法还包括选择第二物理擦除单元并从第二擦除单元读取数据。 该方法还包括根据从第二物理擦除单元读取的数据确定在第二物理擦除单元是否发生数据错误，并且如果发生数据错误，则选择第三物理擦除单元，校正从第二物理擦除单元读取的数据 擦除单元以产生校正数据并将校正的数据写入第三物理擦除单元。

公开(公告)号：US09213636B2

公开(公告)日：2015-12-15

申请号：US14558190

申请日：2014-12-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chien-Hua Chu ,  Chih-Kang Yeh

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/14 ,  G06F21/79 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/1408 ,  G06F21/79 ,  G06F2212/7201

Abstract: A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

公开(公告)号：US09177656B2

公开(公告)日：2015-11-03

申请号：US14162783

申请日：2014-01-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10

CPC classification number: G11C16/14 ,  G06F12/0246 ,  G06F2212/7202 ,  G11C16/10 ,  G11C16/16

Abstract: The writing method includes: grouping logical erasing units into a first region and an second region; determining if a first logical erasing unit which a host system intends to write belongs to the first region or the second region; if the first logical erasing unit belongs to the first region, writing data to a spare physical programming unit, wherein the physical erasing unit to which the spare physical programming belongs further stores data belonging to another logical erasing unit; if the first logical erasing unit belongs to the second region, writing data to a physical erasing unit in which all the valid data belong to the first logical erasing unit. Accordingly, a speed of sequential writing is guaranteed to be greater than a target value.

Abstract translation: 写入方法包括：将逻辑擦除单元分组为第一区域和第二区域; 确定主机系统想要写入的第一逻辑擦除单元是否属于第一区域或第二区域; 如果第一逻辑擦除单元属于第一区域，则将数据写入备用物理编程单元，其中备用物理编程所属的物理擦除单元进一步存储属于另一逻辑擦除单元的数据; 如果第一逻辑擦除单元属于第二区域，则将数据写入其中所有有效数据属于第一逻辑擦除单元的物理擦除单元。 因此，顺序写入的速度保证大于目标值。