公开(公告)号：US20230253393A1

公开(公告)日：2023-08-10

申请号：US18301939

申请日：2023-04-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jonghwan BAEK ,  JeongHyuk PARK ,  Seungwon IM ,  Keunhyuk LEE

IPC: H01L25/18 ,  H01L23/495 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/49524 ,  H01L23/3677 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/33 ,  H01L25/50 ,  H01L23/49575 ,  H01L2224/33181 ,  H01L2224/32245

Abstract: Described implementations provide wireless, surface mounting of at least two semiconductor die on die attach pads (DAPs) of the semiconductor package, where the at least two semiconductor die are electrically connected by a clip. A stress buffer layer may be provided on the clip, and a heatsink may be provided on the stress buffer layer. The heatsink may be secured with an external mold material.

公开(公告)号：US20230225044A1

公开(公告)日：2023-07-13

申请号：US18154303

申请日：2023-01-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Seungwon IM ,  Roveendra PAUL ,  Jerome TEYSSEYRE

IPC: H05K1/02 ,  H05K1/18 ,  H03K17/687

CPC classification number: H05K1/0216 ,  H05K1/181 ,  H03K17/6871 ,  H05K2201/10166 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: In general aspect, a module can include a substrate having a semiconductor circuit implemented thereon, and a negative power supply terminal electrically coupled with the semiconductor circuit via the substrate. The negative power supply terminal includes a connection tab arranged in a first plane. The module also includes a first positive power supply terminal electrically and a second positive power supply terminal that are coupled with the semiconductor circuit via the substrate. The first positive power supply terminal being laterally disposed from the negative power supply terminal, and including a connection tab arranged in the first plane. The second positive power supply terminal is laterally disposed from the negative power supply terminal and arranged in the first plane, such that the negative power supply terminal is disposed between the first positive power supply terminal and the second positive power supply terminal.

公开(公告)号：US20230075519A1

公开(公告)日：2023-03-09

申请号：US18055139

申请日：2022-11-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Maria Cristina ESTACIO ,  Seungwon IM

IPC: H01L23/495 ,  H01L23/00 ,  H01L29/16 ,  H01L23/473 ,  H01L23/433 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56

Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

公开(公告)号：US20210265175A1

公开(公告)日：2021-08-26

申请号：US17315671

申请日：2021-05-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Keunhyuk LEE ,  Oseob JEON ,  Joonseo SON ,  Seungwon IM

IPC: H01L21/56 ,  H05K3/28 ,  H01L23/498 ,  H01L23/373 ,  H01L23/31 ,  H01L25/07

Abstract: A method can include coupling a semiconductor chip and an electrode with a substrate. Bottom and top mold die can be use, where the top mold die define a first space and a second space that is separated from the first space. The method can include injecting encapsulation material to form an encapsulation member coupled to and covering at least a portion of the substrate. The encapsulation member can include a housing unit housing the electrode. The electrode can have a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate can having a portion exposed within the open space, and the encapsulation member can have an open cross-section perpendicular to an upper surface of the substrate.

公开(公告)号：US20210111104A1

公开(公告)日：2021-04-15

申请号：US16677103

申请日：2019-11-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Seungwon IM ,  JooYang EOM ,  Jerome TEYSSEYRE

IPC: H01L23/495 ,  H01L23/00

Abstract: Implementations of a clip may include a first copper layer directly bonded to a first side of a ceramic layer, a second copper layer directly bonded to a second side of the ceramic layer, the second side of the ceramic layer opposite the first side of the ceramic layer, and a plurality of channels partially etched into a thickness of the second copper layer.

公开(公告)号：US20190122970A1

公开(公告)日：2019-04-25

申请号：US15789254

申请日：2017-10-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Maria Cristina ESTACIO ,  Seungwon IM

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L29/16

Abstract: In a general aspect, an apparatus can include a package including a common gate conductor, a first silicon carbide die having a die gate conductor, and a second silicon carbide die having a die gate conductor. The apparatus can include a first conductive path between the common gate conductor and the die gate conductor of the first silicon carbide die and a second conductive path between the common gate conductor and the die gate conductor of the second silicon carbide die where the first conductive path has a length substantially equal to a length of the second conductive path.