公开(公告)号：US20180315681A1

公开(公告)日：2018-11-01

申请号：US15714539

申请日：2017-09-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON ,  Byoungok LEE ,  Yoonsoo LEE ,  Joonseo SON ,  Dukyong LEE ,  Changyoung PARK

IPC: H01L23/433 ,  H01L23/24 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13

Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

公开(公告)号：US20210265175A1

公开(公告)日：2021-08-26

申请号：US17315671

申请日：2021-05-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Keunhyuk LEE ,  Oseob JEON ,  Joonseo SON ,  Seungwon IM

IPC: H01L21/56 ,  H05K3/28 ,  H01L23/498 ,  H01L23/373 ,  H01L23/31 ,  H01L25/07

Abstract: A method can include coupling a semiconductor chip and an electrode with a substrate. Bottom and top mold die can be use, where the top mold die define a first space and a second space that is separated from the first space. The method can include injecting encapsulation material to form an encapsulation member coupled to and covering at least a portion of the substrate. The encapsulation member can include a housing unit housing the electrode. The electrode can have a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate can having a portion exposed within the open space, and the encapsulation member can have an open cross-section perpendicular to an upper surface of the substrate.

公开(公告)号：US20220093487A1

公开(公告)日：2022-03-24

申请号：US17457100

申请日：2021-12-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON ,  Byoungok LEE ,  Yoonsoo LEE ,  Joonseo SON ,  Dukyong LEE ,  Changyoung PARK

IPC: H01L23/433 ,  H01L23/13 ,  H01L23/473 ,  H01L23/498 ,  H01L25/065 ,  H01L23/495

Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

公开(公告)号：US20240234246A1

公开(公告)日：2024-07-11

申请号：US18616351

申请日：2024-03-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON ,  Byoungok LEE ,  Yoonsoo LEE ,  Joonseo SON ,  Dukyong LEE ,  Changyoung PARK

IPC: H01L23/433 ,  H01L23/13 ,  H01L23/24 ,  H01L23/473 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/433 ,  H01L23/13 ,  H01L23/4334 ,  H01L23/473 ,  H01L23/49568 ,  H01L23/49861 ,  H01L25/0657 ,  H01L23/24 ,  H01L2224/33

Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

公开(公告)号：US20180254262A1

公开(公告)日：2018-09-06

申请号：US15449473

申请日：2017-03-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Mankyo JONG ,  ByoungOk LEE ,  Joonseo SON ,  Oseob JEON

IPC: H01L25/065 ,  H01L23/31 ,  H01L29/739

CPC classification number: H02M7/003 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49537 ,  H01L23/498 ,  H01L24/33 ,  H01L25/072

Abstract: In a general aspect, an apparatus can include a first substrate operatively coupled with a second substrate. The apparatus can also include a power supply terminal assembly including a first power supply terminal aligned along a first plane, the first power supply terminal being electrically coupled with the first substrate. The power supply terminal assembly can also include a second power supply terminal aligned along a second plane, the second power supply terminal being electrically coupled with the second substrate. The power supply terminal assembly can further include a power supply terminal frame having an isolation portion disposed between the first power supply terminal and the second power supply terminal and a retention portion disposed around a portion of the first power supply terminal and disposed around a portion of the second power supply terminal.

公开(公告)号：US20250149512A1

公开(公告)日：2025-05-08

申请号：US19019150

申请日：2025-01-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Mankyo JUNG ,  Joonseo SON ,  Oseob JEON ,  Olaf ZSCHIESCHANG

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/051 ,  H01L23/31 ,  H01L23/373 ,  H01L23/538 ,  H01L25/07

Abstract: Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.

公开(公告)号：US20200185305A1

公开(公告)日：2020-06-11

申请号：US16790933

申请日：2020-02-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON ,  Byoungok LEE ,  Yoonsoo LEE ,  Joonseo SON ,  Dukyong LEE ,  Changyoung PARK

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13 ,  H01L23/495 ,  H01L23/473

Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.