EMI Shielding for Flip Chip Package with Exposed Die Backside

    公开(公告)号:US20200051926A1

    公开(公告)日:2020-02-13

    申请号:US16529486

    申请日:2019-08-01

    Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.

    Semiconductor device and method of forming electrical circuit pattern within encapsulant of SIP module

    公开(公告)号:US11923260B2

    公开(公告)日:2024-03-05

    申请号:US18154993

    申请日:2023-01-16

    CPC classification number: H01L23/31 H01L21/565 H01L23/60 H01L23/66

    Abstract: A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

    Semiconductor Device and Method of Heat Dissipation Using Graphene

    公开(公告)号:US20240014093A1

    公开(公告)日:2024-01-11

    申请号:US17810901

    申请日:2022-07-06

    CPC classification number: H01L23/3672 H01L23/373 H01L23/4334

    Abstract: A semiconductor device has a first substrate and electrical component disposed over the first substrate. A graphene layer is disposed over the electrical component, and a thermal interface material is disposed between the graphene layer. A heat sink is disposed over the thermal interface material. The graphene layer, in combination with the thermal interface material, aids with the heat transfer between the electrical component and heat sink. The graphene layer may be disposed over a second substrate made of copper. An encapsulant is deposited over the first substrate and around the electrical component and graphene substrate. The thermal interface material and heat sink may extend over the encapsulant. The heat sink can have vertical or angled extensions from the horizontal portion of the heat sink down to the substrate. The heat sink can extend over multiple modules.

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