公开(公告)号：US20160293655A1

公开(公告)日：2016-10-06

申请号：US15083755

申请日：2016-03-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi YONEDA ,  Takuro OHMARU ,  Yuki OKAMOTO

IPC: H01L27/146 ,  H01L31/0272 ,  H01L29/786

CPC classification number: H01L27/14643 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14641 ,  H01L27/14665 ,  H01L29/7869 ,  H01L31/02005 ,  H01L31/022408 ,  H01L31/0272 ,  H01L31/107

Abstract: To provide an imaging device capable of high-speed reading. The imaging device includes a photodiode, a first transistor, a second transistor, a third transistor, and a fourth transistor. The back gate electrode of the first transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the first transistor and a potential lower than the source potential of the first transistor. The back gate electrode of the second transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the second transistor. The back gate electrode of the third transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the third transistor and a potential lower than the source potential of the third transistor.

Abstract translation: 提供能够进行高速读取的成像装置。 成像装置包括光电二极管，第一晶体管，第二晶体管，第三晶体管和第四晶体管。 第一晶体管的背栅电极电连接到可以提供高于第一晶体管的源极电位的电位和低于第一晶体管的源极电位的电位的布线。 第二晶体管的背栅极电连接到可以提供高于第二晶体管的源极电位的电位的布线。 第三晶体管的背栅电极电连接到可以提供高于第三晶体管的源极电位的电位和低于第三晶体管的源极电位的电位的布线。

公开(公告)号：US20140340073A1

公开(公告)日：2014-11-20

申请号：US14275015

申请日：2014-05-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki OKAMOTO ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa

IPC: G01R19/25 ,  H03K17/16

CPC classification number: H03K17/162 ,  G01R19/252 ,  G01R31/2621

Abstract: A signal processing device and a measuring method are provided. A ring oscillator includes (2n+1) signal transmission circuits (n is an integer greater than or equal to 1). One of the signal transmission circuits comprises an inverter, a first transistor, and a second transistor; one of an input terminal and an output terminal of the inverter is connected to one of a source and a drain of the first transistor; one of a source and a drain of the second transistor is connected to a gate of the first transistor; an output of a k-th (k is an integer greater than or equal to 1 and less than or equal to 2n) signal transmission circuit is connected to an input of a (k+1)-th signal transmission circuit; and an output of a (2n+1)-th signal transmission circuit is connected to an input of a first signal transmission circuit.

Abstract translation: 提供信号处理装置和测量方法。 环形振荡器包括（2n + 1）个信号传输电路（n是大于或等于1的整数）。 信号传输电路之一包括反相器，第一晶体管和第二晶体管; 逆变器的输入端子和输出端子之一连接到第一晶体管的源极和漏极之一; 第二晶体管的源极和漏极之一连接到第一晶体管的栅极; 信号发送电路的第k（k为1以上且小于等于2n的整数）的输出连接到第（k + 1）个信号发送电路的输入端; 并且第（2n + 1）个信号传输电路的输出连接到第一信号传输电路的输入端。

公开(公告)号：US20250157404A1

公开(公告)日：2025-05-15

申请号：US19021338

申请日：2025-01-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Susumu KAWASHIMA ,  Yutaka OKAZAKI

IPC: G09G3/3233 ,  H10D84/83 ,  H10D86/40 ,  H10D86/60

Abstract: The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M2) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M1), the second switch (M3) and the first capacitor (C1) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M4), the second capacitor (C2) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M6) and a drain of the second transistor (M5), a gate of the second transistor is electrically connected to the fifth switch (M7), the third capacitor (C3) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element (61).

公开(公告)号：US20250040397A1

公开(公告)日：2025-01-30

申请号：US18704237

申请日：2022-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI ,  Yuki OKAMOTO

IPC: H10K59/65 ,  G02B27/01 ,  H10K50/19 ,  H10K59/121 ,  H10K59/131

Abstract: An object of the present invention is to provide a display apparatus that reduces the amount of image data transmitted and maintains high-level display quality, which is a display apparatus (Dp) including a display portion (DIS), a light-emitting portion (SHB), and a light-receiving portion (SJB). The display portion includes a first display region (ALP) and a first circuit region that overlap with each other. The first display region includes a plurality of first display pixels and the first circuit region includes a first driver circuit (DRV). The first driver circuit is electrically connected to the plurality of first display pixels through a plurality of first wirings extended in the first display region. The light-emitting portion has a function of emitting first light, and the light-receiving portion has a function of receiving second light that is reflected by irradiation of an object with the first light and a function of generating information based on the second light. The first driver circuit has a function of, in accordance with the information, one of transmitting a plurality of image signals to the plurality of first wirings and transmitting the same image signal to two or more consecutive adjacent wirings among the plurality of first wirings.

公开(公告)号：US20250040144A1

公开(公告)日：2025-01-30

申请号：US18780650

申请日：2024-07-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takanori MATSUZAKI ,  Yuto YAKUBO ,  Yuki OKAMOTO

IPC: H10B51/20 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78 ,  H01L29/786 ,  H10B51/10 ,  H10B53/10 ,  H10B53/20

Abstract: A memory device with a novel structure. A first transistor includes a first oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, and a second insulating layer. A second transistor includes a second oxide semiconductor layer, the first conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, a third insulating layer, and a fourth insulating layer. In a plan view, the first oxide semiconductor layer includes a region facing the first conductive layer with the first insulating layer therebetween and a region facing the second conductive layer with the second insulating layer therebetween. In a plan view, the second oxide semiconductor layer includes a region facing the fifth conductive layer with the third insulating layer therebetween and a region facing the sixth conductive layer with the fourth insulating layer therebetween. The first oxide semiconductor layer is provided in contact with the third conductive layer and the fourth conductive layer. The second oxide semiconductor layer is provided in contact with the first conductive layer and the seventh conductive layer. In a cross-sectional view, the third conductive layer includes a region overlapping with the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer.

公开(公告)号：US20240250097A1

公开(公告)日：2024-07-25

申请号：US18438633

申请日：2024-02-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA ,  Hiroki INOUE ,  Takuro OHMARU

IPC: H01L27/146 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H01L31/075 ,  H04N23/54

CPC classification number: H01L27/14603 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/146 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14692 ,  H01L29/7869 ,  H01L31/075 ,  H04N23/54 ,  H01L23/5286

Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.

公开(公告)号：US20240161695A1

公开(公告)日：2024-05-16

申请号：US18282164

申请日：2022-03-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Minato ITO ,  Takanori MATSUZAKI ,  Munehiro KOZUMA ,  Yuki OKAMOTO ,  Yusuke KOUMURA

IPC: G09G3/3233 ,  H10K59/131

CPC classification number: G09G3/3233 ,  H10K59/131 ,  G09G2300/0809 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2340/0442

Abstract: A display apparatus with a novel structure is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a driver circuit region, and the second layer includes a pixel array. The pixel array includes a plurality of pixel regions. The driver circuit region includes a control circuit unit and a plurality of local driver circuits. One of the plurality of local driver circuits corresponds to any one of the plurality of pixel regions. The local driver circuit has a function of outputting a driving signal for driving a plurality of pixels included in the corresponding pixel region. The control circuit unit has a function of comparing definition data of an input image signal and aspect ratio data of the pixel array to determine a first region where display is performed and a second region where display is not performed, and outputting, to the local driver circuit corresponding to the second region, a control signal for stopping output of the driving signal.

公开(公告)号：US20230337439A1

公开(公告)日：2023-10-19

申请号：US18028812

申请日：2021-10-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Kousuke SASAKI

IPC: H10B53/30 ,  H10B53/40 ,  G11C11/22

CPC classification number: H10B53/30 ,  H10B53/40 ,  G11C11/221 ,  G11C11/2273

Abstract: Provided is a semiconductor device capable of reading data with high accuracy. The semiconductor device includes first and second memory cells and a switch. The first memory cell includes first and second transistors and a first capacitor, and the second memory cell includes third and fourth transistors and a second capacitor. The first and second capacitors each include a ferroelectric layer between a pair of electrodes. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and the gate of the second transistor is electrically connected to one of the electrodes of the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor, and the gate of the fourth transistor is electrically connected to one of the electrodes of the second capacitor. The other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor via the switch.

公开(公告)号：US20230040508A1

公开(公告)日：2023-02-09

申请号：US17788050

申请日：2020-12-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Masashi OOTA ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  G06N3/02 ,  H01L29/423 ,  H01L27/105

Abstract: To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

公开(公告)号：US20220329233A1

公开(公告)日：2022-10-13

申请号：US17836283

申请日：2022-06-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Kei TAKAHASHI

IPC: H03K3/0233 ,  H01M10/48 ,  H02J7/02 ,  H03K17/22 ,  H03K19/0185 ,  G06G7/186 ,  H03K5/08 ,  H03K19/20

Abstract: To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.