公开(公告)号：US12197730B2

公开(公告)日：2025-01-14

申请号：US17848159

申请日：2022-06-23

Applicant: Texas Instruments Incorporated

Inventor： Vignesh Raghavendra ,  Srirama Govindarajan ,  Mihir Mody ,  Prithvi Y. A.

IPC: G06F3/06

Abstract: An example device includes: a compute core configured to: send a first request to flash manager circuitry, the first request to store write data in a flash memory; and send a second request to the flash manager circuitry, the second request sent after the first request, the second request to transfer an XIP read operation to the flash memory; the flash manager circuitry configured to: receive the first request; transmit the write data to the flash memory for storing in the flash memory; receive the second request before the storing of the write data is complete; determine whether to preempt the storing of the write data, transmit, in response to a determination to preempt, the XIP read operation to the flash; and the flash memory configured to provide data to the compute core based on the transmitted XIP read operation.

公开(公告)号：US12105653B2

公开(公告)日：2024-10-01

申请号：US18190242

申请日：2023-03-27

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F9/4881 ,  G06F13/1673 ,  G06F13/4027 ,  G06F2213/0038

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.

公开(公告)号：US20240289920A1

公开(公告)日：2024-08-29

申请号：US18175697

申请日：2023-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hrushikesh Garud ,  Mihir Mody ,  Rajasekhar Allu ,  Jing-Fei Ren ,  Niraj Nandan

IPC: G06T3/40 ,  G06T1/20 ,  G06T7/00

CPC classification number: G06T3/4015 ,  G06T1/20 ,  G06T7/0002 ,  G06T2207/10024 ,  G06T2207/10048 ,  G06T2207/20004 ,  G06T2207/20084

Abstract: Various embodiments disclosed herein relate to pixel pattern conversion, and more specifically to using an adaptive filter to convert complex pixel data to non-complex pixel formats. An image processing pipeline is provided herein that comprises an upstream component, a pattern conversion component downstream with respect to the upstream component in the image processing pipeline, and a downstream component relative to the pattern conversion component. The pattern conversion component is configured to obtain RGB-IR pixel data produced by the upstream component of the image processing pipeline, convert the RGB-IR pixel data into RGB pixel data and IR pixel data using an adaptive filter, and supply the RGB pixel data and the IR pixel data to the downstream component of the image processing pipeline.

公开(公告)号：US12050542B2

公开(公告)日：2024-07-30

申请号：US18345098

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajat Sagar

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/28

Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.

公开(公告)号：US20240192884A1

公开(公告)日：2024-06-13

申请号：US18585619

申请日：2024-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Mihir Mody

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/28 ,  G06F2213/28

Abstract: Various systems and circuits are provided. One such system includes input interfaces to receive items of input data of different types; output interfaces, each of a different type; an interconnect coupled to the input interfaces and to the output interfaces; and an multichip hub that includes buffers respectively corresponding to the types of input data, context memory blocks, and a data movement engine with a context mapper to determine a context of each item of input data received and provide the item of input data to a corresponding context memory block. Multiple processing blocks within the multichip hub are each configured to perform a respective processing operation. The data movement engine receives context configuration data to determine, for each item of input data received, which of the multiple processing operations are to be applied to the item of input data.

公开(公告)号：US20230418472A1

公开(公告)日：2023-12-28

申请号：US17848159

申请日：2022-06-23

Applicant: Texas Instruments Incorporated

Inventor： Vignesh Raghavendra ,  Srirama Govindarajan ,  Mihir Mody ,  Prithvi Y.A.

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/0632

Abstract: An example device includes: a compute core configured to: send a first request to flash manager circuitry, the first request to store write data in a flash memory; and send a second request to the flash manager circuitry, the second request sent after the first request, the second request to transfer an XIP read operation to the flash memory; the flash manager circuitry configured to: receive the first request; transmit the write data to the flash memory for storing in the flash memory; receive the second request before the storing of the write data is complete; determine whether to preempt the storing of the write data, transmit, in response to a determination to preempt, the XIP read operation to the flash; and the flash memory configured to provide data to the compute core based on the transmitted XIP read operation.

公开(公告)号：US11763513B2

公开(公告)日：2023-09-19

申请号：US17028389

申请日：2020-09-22

Applicant: Texas Instruments Incorporated

Inventor： Mihir Mody ,  Hemant Hariyani ,  Anand Balagopalakrishnan ,  Jason Jones ,  Ajay Jayaraj ,  Manoj Koul

IPC: G06T15/00 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T2200/28 ,  G06T2210/52

Abstract: A method and system for dynamically transferring graphical image processing operations from a graphical processing unit (GPU) to a digital signal processor (DSP). The method includes estimating the number of operations needed for the processing a set of image data; determining the operational limits of a GPU and compare with estimated number of operations and if the operational limits are exceeded; transfer the processing operations to the DSP from the GPU. The transfer can include transferring a portion of executable code for performing the processing operations, and generating a replacement code for the GPU. The DSP can then process a portion of the image data before sending it to the GPU for further processing.

公开(公告)号：US10747692B2

公开(公告)日：2020-08-18

申请号：US16234508

申请日：2018-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Brian Chae ,  Rajasekhar Reddy Allu ,  Jason A. T. Jones ,  Anthony Lell ,  Anish Reghunath

IPC: G06F13/16 ,  G06T1/20 ,  H04N5/765 ,  G06F13/28

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

公开(公告)号：US20190244051A1

公开(公告)日：2019-08-08

申请号：US16386723

申请日：2019-04-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anish Reghunath ,  Hetul Sanghvi ,  Michael Lachmayr ,  Mihir Mody

IPC: G06K9/46 ,  G06K9/62

CPC classification number: G06K9/4642 ,  G06K9/00791 ,  G06K9/4661 ,  G06K9/481 ,  G06K9/52 ,  G06K9/6202

Abstract: Systems and methods for performing Census Transforms that includes an input from an image, with a support window created within the image, and a kernel within the support window. The Census Transform calculations and comparisons are performed within the kernel windows. A new Census Transform is disclosed which always inverts a previously made comparison. This new approach can be demonstrated to be equivalent to, applying the original Census Transform, on a pre-processed input kernel, where the pre-processing step adds a fractional position index to each pixel within the N×N kernel. The fractional positional index ensures that no two pixels are equal to one another, and thereby makes the Original Census algorithm on pre-processed kernel same as the new Census algorithm on original kernel. The hardware design for this new Census Transform kernel allows for an always invert of previous comparison system resulting in reduced hardware and power consumption.

公开(公告)号：US10089172B2

公开(公告)日：2018-10-02

申请号：US14587878

申请日：2014-12-31

Applicant: Texas Instruments Incorporated

Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

IPC: G06F11/10 ,  G11C29/52

Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.