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    Microneedle array module and method of fabricating the same
    52.
    发明申请
    Microneedle array module and method of fabricating the same 失效

    公开(公告)号：US20020155737A1

    公开(公告)日：2002-10-24

    申请号：US10162848

    申请日：2002-06-05

    Applicant: The Cleveland Clinic Foundation

    Inventor： Shuvo Roy ,  Aaron J. Fleischman

    IPC: H01R012/00

    CPC classification number: B81C1/00111 ,  A61M37/0015 ,  A61M2037/003 ,  A61M2037/0038 ,  A61M2037/0053 ,  B81B2201/055

    Abstract: A microneedle array module is disclosed comprising a multiplicity of microneedles affixed to and protruding outwardly from a front surface of a substrate to form the array, each microneedle of the array having a hollow section which extends through its center to an opening in the tip thereof. The substrate includes an array of holes which align with the hollow sections of the microneedles and extend through the substrate to a back surface thereof, whereby a liquid applied to the back surface of the substrate may be forced through the holes in the substrate and out through the tips of the microneedle array thereof. In one embodiment, the substrate includes a reservoir well in the back surface thereof. The well extends over the array of holes in the back surface and may be covered by a layer of material which is affixed to the back surface peripheral the well, the layer including an interconnecting passageway to the well. A method of fabricating the microneedle array module is also disclosed comprising the steps of: providing etch resistant mask layers to one and another opposite surfaces of a substrate to predetermined thicknesses; patterning the etch resistant mask layer of the one surface for outer dimensions of the microneedles of the array; patterning the etch resistant mask layer of the other surface for inner dimensions of the microneedles of the array; etching unmasked portions of the substrate from one and the other surfaces to first and second predetermined depths, respectively; and removing the mask layers from the one and the other surfaces. One embodiment of the method includes the steps of: providing an etch resistant mask layer to the other surface of the substrate to a predetermined thickness; patterning the etch resistant mask layer of the other surface to define a reservoir region in the substrate; and etching away the unmasked reservoir region of the substrate to form a reservoir well in the other surface of the substrate. A layer of material may be provided to the other surface to enclose the reservoir well and a passageway is provided through the layer to the well region.

    METHOD AND STRUCTURE OF THREE DIMENSIONAL CMOS TRANSISTORS WITH HYBRID CRYSTAL ORIENTATIONS
    58.
    发明申请
    METHOD AND STRUCTURE OF THREE DIMENSIONAL CMOS TRANSISTORS WITH HYBRID CRYSTAL ORIENTATIONS 有权
    具有混合晶体取向的三维CMOS晶体管的方法与结构

    公开(公告)号：US20150270180A1

    公开(公告)日：2015-09-24

    申请号：US14218633

    申请日：2014-03-18

    Applicant: XIAO (CHARLES) YANG

    Inventor： XIAO (CHARLES) YANG

    IPC: H01L21/8238 ,  H01L29/04

    CPC classification number: H01L21/823878 ,  A61B5/14514 ,  B81B2201/025 ,  B81B2201/055 ,  B81C1/00246 ,  G01L9/0042 ,  G01L9/0054 ,  G01P15/0802 ,  G01P15/125 ,  H01L21/76254 ,  H01L21/8221 ,  H01L25/0657 ,  H01L27/0688 ,  H01L29/045 ,  H01L2924/0002 ,  H03H3/0073 ,  H01L2924/00

    Abstract: A method for fabricating a three-dimensional integrated circuit device includes providing a first substrate having a first crystal orientation, forming at least one or more PMOS devices overlying the first substrate, and forming a first dielectric layer overlying the one or more PMOS devices. The method also includes providing a second substrate having a second crystal orientation, forming at least one or more NMOS devices overlying the second substrate, and forming a second dielectric layer overlying the one or more NMOS devices. The method further includes coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate.

    Abstract translation: 一种制造三维集成电路器件的方法包括提供具有第一晶体取向的第一衬底，形成覆盖在第一衬底上的至少一个或多个PMOS器件，以及形成覆盖该一个或多个PMOS器件的第一介电层。 该方法还包括提供具有第二晶体取向的第二衬底，形成覆盖第二衬底的至少一个或多个NMOS器件，以及形成覆盖该一个或多个NMOS器件的第二电介质层。 该方法还包括将第一电介质层耦合到第二电介质层以形成包括覆盖在第二衬底上的第一衬底的混合结构。

    Out-of plane microneedle manufacturing process
    59.
    发明授权
    Out-of plane microneedle manufacturing process 有权
    平面微针制造工艺

    公开(公告)号：US08999177B2

    公开(公告)日：2015-04-07

    申请号：US12808334

    申请日：2008-10-17

    Applicant: Astrid Cachemaille ,  Francois Cannehan

    Inventor： Astrid Cachemaille ,  Francois Cannehan

    IPC: C25F3/00 ,  B44C1/22 ,  C03C15/00 ,  B81C1/00 ,  A61M37/00

    CPC classification number: A61M37/0015 ,  A61M2037/0053 ,  B81B2201/055 ,  B81C1/00111 ,  Y10T29/49826 ,  Y10T428/24479

    Abstract: Out-of-plane microneedle manufacturing process comprising the simultaneous creation of a network of microneedles and the creation of a polygonal shaped hat (2) above each microneedle (1) under formation, said process comprising the following steps: providing bridges (3) between the hats (3), maintaining the bridges (3) during the remaining microneedle manufacturing steps, removing the bridges (3), together with the hats (2), when the microneedles (1) are formed.

    Abstract translation: 面外微型制造工艺包括同时创建微针网络并在形成每个微针（1）上方形成多边形帽（2），所述方法包括以下步骤：提供桥 （3），在剩余的微针制造步骤期间保持桥（3），当形成微针（1）时，与帽子（2）一起移除桥（3）。

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