公开(公告)号：US20160118265A1

公开(公告)日：2016-04-28

申请号：US14988895

申请日：2016-01-06

Applicant: The Board of Trustees of the University of Illinois

Inventor： Lynford Goddard ,  Kaiyuan Wang ,  Chris Edwards ,  Lonna Edwards ,  Xin Yu ,  Gang Logan Liu ,  Samuel Washington ,  Shailendra Srivastava ,  Terry Koker ,  Julianne Lee ,  Catherine Britt Carlson

IPC: H01L21/306 ,  H01L31/0236 ,  H01L21/768 ,  H01L31/0232

CPC classification number: H01L21/30604 ,  B81C1/00103 ,  B81C1/00111 ,  B81C1/00119 ,  B81C1/00214 ,  B81C1/00484 ,  B81C1/00539 ,  B81C1/00595 ,  B81C2201/0114 ,  B81C2201/0139 ,  B81C2201/0157 ,  C25F3/12 ,  C25F3/14 ,  G01B11/2441 ,  H01L21/30617 ,  H01L21/3063 ,  H01L21/76886 ,  H01L22/12 ,  H01L31/02327 ,  H01L31/02363

Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. An electrical potential is applied across the interface of the semiconductor and the solution with a specified temporal profile relative to the temporal profile of the spatial pattern of illumination. Such methods are applied to the fabrication of a photodetector integral with a parabolic reflector, cell size sorting chips, a three-dimensional photonic bandgap chip, a photonic integrated circuit, and an integrated photonic microfluidic circuit.

Abstract translation: 用于相对于衬底的表面相对地制造三维结构并用于在表面上相加地沉积金属和掺杂剂原子并将其扩散到本体中的方法和装置。 将化学溶液施加到半导体衬底的表面，并且通过将在特定强度，波长和持续时间上的特定的照明的空间图案投影在多个像素的每个像素上来产生电子 - 空穴对的空间图案 表面。 相对于照明的空间模式的时间分布，电势跨越半导体和解决方案的界面以特定的时间分布被施加。 这种方法适用于与抛物面反射器，单元尺寸分选芯片，三维光子带隙芯片，光子集成电路和集成光子微流体电路集成的光电检测器的制造。

公开(公告)号：US09096427B2

公开(公告)日：2015-08-04

申请号：US14286175

申请日：2014-05-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Sofiane Ben Mbarek ,  Sophie Giroud ,  Frederic-Xavier Gaillard

IPC: H01L21/00 ,  B81C1/00

CPC classification number: B81C1/00531 ,  B81B2203/0118 ,  B81C1/0015 ,  B81C1/00539 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/014 ,  B81C2201/019 ,  B81C2203/036

Abstract: Method for making at least one first suspended part of a microelectronic or nanoelectronic structure from a monolithic part of a first substrate, the method comprising the following steps: make a first etching with a first given depth in the monolithic substrate to define the suspended part, deposit a protective layer on at least the side edges of the first etching, make a second etching with a second depth in the first etching, make a physicochemical treatment of at least part of the zone located under the suspended structure so as to modify it, and release the suspended part by removal of the physicochemically treated part.

Abstract translation: 用于从第一衬底的整体部分制造微电子或纳米电子结构的至少一个第一悬浮部分的方法，所述方法包括以下步骤：在所述整体式衬底中进行第一给定深度的第一蚀刻以限定所述悬浮部分， 在第一蚀刻的至少侧边缘上沉积保护层，在第一蚀刻中进行具有第二深度的第二蚀刻，对位于悬挂结构下方的区域的至少一部分进行物理化学处理，以进行改性， 并通过去除物理化学处理的部分释放悬浮的部分。

公开(公告)号：US20140357006A1

公开(公告)日：2014-12-04

申请号：US14286175

申请日：2014-05-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Sofiane BEN MBAREK ,  Sophie Giroud ,  Frederic-Xavier Gaillard

IPC: B81C1/00

CPC classification number: B81C1/00531 ,  B81B2203/0118 ,  B81C1/0015 ,  B81C1/00539 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/014 ,  B81C2201/019 ,  B81C2203/036

Abstract: Method for making at least one first suspended part of a microelectronic or nanoelectronic structure from a monolithic part of a first substrate, the method comprising the following steps: make a first etching with a first given depth in the monolithic substrate to define the suspended part, deposit a protective layer on at least the side edges of the first etching, make a second etching with a second depth in the first etching, make a physicochemical treatment of at least part of the zone located under the suspended structure so as to modify it, and release the suspended part by removal of the physicochemically treated part.

Abstract translation: 用于从第一衬底的整体部分制造微电子或纳米电子结构的至少一个第一悬浮部分的方法，所述方法包括以下步骤：在所述整体式衬底中进行第一给定深度的第一蚀刻以限定所述悬浮部分， 在第一蚀刻的至少侧边缘上沉积保护层，在第一蚀刻中进行具有第二深度的第二蚀刻，对位于悬挂结构下方的区域的至少一部分进行物理化学处理，以进行改性， 并通过去除物理化学处理的部分释放悬浮的部分。

公开(公告)号：US08288192B2

公开(公告)日：2012-10-16

申请号：US12918660

申请日：2009-04-28

Applicant: Chienliu Chang

Inventor： Chienliu Chang

IPC: H01L21/00

CPC classification number: B06B1/0292 ,  B81B2201/038 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/00476 ,  B81C2201/0114

Abstract: In a method of manufacturing a capacitive electromechanical transducer, a first electrode (8) is formed on a substrate (4), an insulating layer (9) which has an opening (6) leading to the first electrode is formed on the first electrode (8), and a sacrificial layer is formed on the insulating layer. A membrane (3) having a second electrode (1) is formed on the sacrificial layer, and an aperture is provided as an etchant inlet in the membrane. The sacrificial layer is etched to form a cavity (10), and then the aperture serving as an etchant inlet is sealed. The etching is executed by electrolytic etching in which a current is caused to flow between the first electrode (8) and an externally placed counter electrode through the opening (6) and the aperture of the membrane.

Abstract translation: 在制造电容式机电换能器的方法中，在基板（4）上形成第一电极（8），在第一电极上形成具有通向第一电极的开口（6）的绝缘层（9） 8），并且在绝缘层上形成牺牲层。 在牺牲层上形成具有第二电极（1）的膜（3），并且在膜中设置有作为蚀刻剂入口的孔。 蚀刻牺牲层以形成空腔（10），然后密封用作蚀刻剂入口的孔。 蚀刻通过电解蚀刻进行，其中使电流通过开口（6）和膜的孔径在第一电极（8）和外部放置的对电极之间流动。

公开(公告)号：US20110253544A1

公开(公告)日：2011-10-20

申请号：US13133378

申请日：2009-12-08

Applicant: Dusan Losic

Inventor： Dusan Losic

IPC: C25D5/18 ,  C25D11/02 ,  C25D21/12 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: C25D1/08 ,  B81C1/00047 ,  B81C2201/0114 ,  B81C2201/0115 ,  C25D1/00 ,  C25D1/006 ,  C25D11/02 ,  C25D11/045

Abstract: A process for forming a porous metal oxide or metalloid oxide material, the process including: providing an anodic substrate including a metal or metalloid substrate; providing a cathodic substrate; contacting the anodic substrate and the cathodic substrate with an acid electrolyte to form an electrochemical cell; applying an electrical signal to the electrochemical cell; and forming shaped pores in the metal or metalloid substrate by: (c) time varying the applied voltage of the electrical signal to provide a voltage cycle having a minimum voltage period during which a minimum voltage is applied, a maximum voltage period during which a maximum voltage is applied, and a transition period between the minimum voltage period and the maximum voltage period, wherein the voltage is progressively increased from the minimum voltage to the maximum voltage during the transition period, or (d) time varying the current of the electrical signal to provide a current cycle having a minimum current period during which a minimum current is applied, a maximum current period during which a maximum current is applied, and a transition period between the minimum current period and the maximum current period, wherein the voltage is progressively increased from the minimum current to the maximum current during the transition period.

Abstract translation: 一种形成多孔金属氧化物或准金属氧化物材料的方法，该方法包括：提供包含金属或准金属基质的阳极底物; 提供阴极底物; 使阳极底物和阴极底物与酸性电解质接触以形成电化学电池; 向电化学电池施加电信号; 以及通过以下步骤在所述金属或准金属基体中形成成形孔：（c）对所述电信号的施加电压进行时变，以提供具有施加最小电压的最小电压周期的电压周期，其中最大电压周期 施加电压，以及在最小电压周期和最大电压周期之间的过渡期间，其中电压在过渡期间从最小电压逐渐增加到最大电压，或（d）时变电流信号的电流 以提供具有施加最小电流的最小电流周期，施加最大电流的最大电流周期以及最小电流周期与最大电流周期之间的转变周期的电流周期，其中电压逐渐变化 在过渡期间从最小电流增加到最大电流。

公开(公告)号：US20080044939A1

公开(公告)日：2008-02-21

申请号：US11744971

申请日：2007-05-07

Applicant: Androula Nassiopoulou ,  Grigoris Kaltsas ,  Dimitrios Pagonis

Inventor： Androula Nassiopoulou ,  Grigoris Kaltsas ,  Dimitrios Pagonis

IPC: H01L21/02

CPC classification number: G01F1/6888 ,  B81B2201/0278 ,  B81B2203/0338 ,  B81C1/00071 ,  B81C2201/0114 ,  B81C2201/0115 ,  G01F1/6845 ,  G01K7/028

Abstract: This invention provides a miniaturized silicon thermal flow sensor with improved characteristics, based on the use of two series of integrated thermocouples (6, 7) on each side of a heater (4), all integrated on a porous silicon membrane (2) on top of a cavity (3). Porous silicon (2) with the cavity (3) underneath provides very good thermal isolation for the sensor elements, so as the power needed to maintain the heater (4) at a given temperature is very low. The formation process of the porous silicon membrane (2) with the cavity (3) underneath is a two-step single electrochemical process. It is based on the fact that when the anodic current is relatively low, we are in a regime of porous silicon formation, while if this current exceeds a certain value we turn into a regime of electropolishing. The process starts at low current to form porous silicon (2) and it is then turned into electropolishing conditions to form the cavity (3) underneath. Various types of thermal sensor devices, such as flow sensors, gas sensors, IR detectors, humidity sensors and thermoelectric power generators are described using the proposed methodology. Furthermore the present invention provides a method for the formation of microfluidic channels (16) using the same technique of porous silicon (17) and cavity (16) formation.

Abstract translation: 本发明提供了一种基于在加热器（4）的每一侧上使用两个集成的热电偶（6,7）的系列，具有改进的特性的小型化硅热流量传感器，它们全部集成在顶部的多孔硅膜（2）上 的腔（3）。 具有下面的空腔（3）的多孔硅（2）为传感器元件提供了非常好的热隔离，因此将加热器（4）保持在给定温度所需的功率非常低。 多孔硅膜（2）与下面的腔（3）的形成过程是两步单电化学过程。 这是基于以下事实：当阳极电流相对较低时，我们处于多孔硅形成的状态，而如果该电流超过一定值，则我们变成电解抛光的方式。 该工艺以低电流开始形成多孔硅（2），然后转化为电解抛光条件以形成下面的空腔（3）。 使用所提出的方法描述了各种类型的热传感器装置，例如流量传感器，气体传感器，红外探测器，湿度传感器和热电发电机。 此外，本发明提供了使用与多孔硅（17）和空腔（16）相同的技术形成微流体通道（16）的方法。

公开(公告)号：US20050072926A1

公开(公告)日：2005-04-07

申请号：US10502465

申请日：2003-01-16

Applicant: Androula Nassiopoulou ,  Grigoris Kaltsas ,  Dimitrios Pagonis

Inventor： Androula Nassiopoulou ,  Grigoris Kaltsas ,  Dimitrios Pagonis

IPC: G01K13/02 ,  B81B1/00 ,  B81B3/00 ,  B81C1/00 ,  G01F1/684 ,  G01K7/01 ,  G01K7/02 ,  H01L31/00

CPC classification number: B81C1/00071 ,  B81B2201/058 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0114 ,  B81C2201/0115 ,  G01F1/6845 ,  G01K7/028

Abstract: This invention provides a miniaturized silicon thermal flow sensor with improved characteristics, based on the use of two series of integrated thermocouples (6, 7) on each side of a heater (4), all integrated on a porous silicon membrane (2) on top of a cavity (3). Porous silicon (2) with the cavity (3) underneath provides very good thermal isolation for the sensor elements, so as the power needed to maintain the heater (4) at a given temperature is very low. The formation process of the porous silicon membrane (2) with the cavity (3) underneath is a two-step single electrochemical process. It is based on the fact that when the anodic current is relatively low, we are in a regime of porous silicon formation, while if this current exceeds a certain value we turn into a regime of electropolishing. The process starts at low current to form porous silicon (2) and it is then turned into electropolishing conditions to form the cavity (3) underneath. Various types of thermal sensor devices, such as flow sensors, gas sensors, IR detectors, humidity sensors and thermoelectric power generators are described using the proposed methodology. Furthermore the present invention provides a method for the formation of microfluidic channels (16) using the same technique of porous silicon (17) and cavity (16) formation.

Abstract translation: 本发明提供了一种基于在加热器（4）的每一侧上使用两个集成的热电偶（6,7）的系列，具有改进的特性的小型化硅热流量传感器，它们全部集成在顶部的多孔硅膜（2）上 的腔（3）。 具有下面的空腔（3）的多孔硅（2）为传感器元件提供了非常好的热隔离，因此将加热器（4）保持在给定温度所需的功率非常低。 多孔硅膜（2）与下面的腔（3）的形成过程是两步单电化学过程。 这是基于以下事实：当阳极电流相对较低时，我们处于多孔硅形成的状态，而如果该电流超过一定值，则我们变成电解抛光的方式。 该工艺以低电流开始形成多孔硅（2），然后转化为电解抛光条件以形成下面的空腔（3）。 使用所提出的方法描述了各种类型的热传感器装置，例如流量传感器，气体传感器，红外探测器，湿度传感器和热电发电机。 此外，本发明提供了使用与多孔硅（17）和空腔（16）相同的技术形成微流体通道（16）的方法。

公开(公告)号：US20050009374A1

公开(公告)日：2005-01-13

申请号：US10838859

申请日：2004-05-04

Applicant: Jun Gao ,  Michael Sailor ,  Sangeeta Bhatia ,  Christopher Flaim

Inventor： Jun Gao ,  Michael Sailor ,  Sangeeta Bhatia ,  Christopher Flaim

IPC: B81C1/00 ,  C25F3/12 ,  C25F3/14 ,  H01L21/26 ,  H01L21/3063

CPC classification number: B81C1/00515 ,  B81C2201/0114 ,  B81C2201/0115 ,  C25F3/12 ,  C25F3/14 ,  H01L21/3063

Abstract: The invention is directed to methods for direct patterning of silicon. The invention provides the ability to fabricate complex surfaces in silicon with three dimensional features of high resolution and complex detail. The invention is suitable, for example, for use in soft lithography as embodiments of the invention can quickly create a master for use in soft lithography. In an embodiment of the invention, electrochemical etching of silicon, such as a silicon wafer, for example, is conducted while at least a portion of the silicon surface is exposed to an optical pattern. The etching creates porous silicon in the substrate, and removal of the porous silicon layer leaves a three-dimensional structure correlating to the optical pattern.

Abstract translation: 本发明涉及直接图案化硅的方法。 本发明提供了在硅中制造具有高分辨率和复杂细节的三维特征的复杂表面的能力。 本发明适用于例如在软光刻中使用，因为本发明的实施例可以快速地创建用于软光刻的母版。 在本发明的一个实施例中，例如硅的电化学蚀刻被进行，同时硅表面的至少一部分暴露于光学图案。 蚀刻在衬底中产生多孔硅，并且去除多孔硅层留下与光学图案相关的三维结构。

公开(公告)号：US06838297B2

公开(公告)日：2005-01-04

申请号：US09867611

申请日：2001-05-31

Applicant: Tatsuya Iwasaki ,  Tohru Den

Inventor： Tatsuya Iwasaki ,  Tohru Den

IPC: H01J1/304 ,  B81C1/00 ,  B82B3/00 ,  G01N27/403 ,  G01N27/414 ,  G11B5/73 ,  G11B5/855 ,  H01F1/00 ,  H01J9/02 ,  H01L21/3063 ,  H01L21/00 ,  H01J9/04 ,  H01J9/12 ,  H01J9/14

CPC classification number: H01F1/009 ,  B81C1/00087 ,  B81C2201/0114 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/7325 ,  G11B5/743 ,  G11B5/855 ,  G11C2213/81 ,  H01F1/0081 ,  H01J1/304 ,  H01J1/3042 ,  H01J9/025 ,  H01J2201/30469 ,  Y10S977/778 ,  Y10S977/78 ,  Y10S977/939

Abstract: The invention provides a nanostructure including an anodized film including nanoholes. The anodized film is formed on a substrate having a surface including at least one material selected from the group consisting of semiconductors, noble metals, Mn, Fe, Co, Ni, Cu and carbon. The nanoholes are cut completely through the anodized film from the surface of the anodized film to the surface of the substrate. The nanoholes have a first diameter at the surface of the anodized film and a second diameter at the surface of the substrate. The nanoholes are characterized in that either a constriction exists at a location between the surface of the anodized film and the surface of the substrate, or the second diameter is greater than the first diameter.

Abstract translation: 本发明提供纳米结构，其包括包括纳孔的阳极氧化膜。 阳极氧化膜形成在具有包括选自半导体，贵金属，Mn，Fe，Co，Ni，Cu和碳中的至少一种材料的表面的基板上。 通过阳极氧化膜将阳极氧化膜的表面完全切割成纳米孔至基底表面。 纳米孔在阳极氧化膜的表面具有第一直径，在基底表面具有第二直径。 纳米孔的特征在于，在阳极氧化膜的表面和基底的表面之间的位置处存在收缩，或者第二直径大于第一直径。

公开(公告)号：US06737668B2

公开(公告)日：2004-05-18

申请号：US09895464

申请日：2001-07-02

Applicant: Tohru Den ,  Tatsuya Iwasaki

Inventor： Tohru Den ,  Tatsuya Iwasaki

IPC: H01L2906

CPC classification number: B01D71/025 ,  B01D67/0065 ,  B81B2203/0315 ,  B81C1/00031 ,  B81C2201/0114 ,  C04B38/0025 ,  C04B2111/00612 ,  C25D11/045 ,  H01L49/00 ,  C04B35/10 ,  C04B38/0003 ,  C04B41/4564

Abstract: A method of manufacturing a structure with pores which are formed by anodic oxidation and whose layout, pitch, position, direction, shape and the like can be controlled. The method includes the steps of: disposing a lamination film on a substrate, the lamination film being made of insulating layers and a layer to be anodically oxidized and containing aluminum as a main composition; and performing anodic oxidation starting from an end surface of the lamination film to form a plurality of pores having an axis substantially parallel to a surface of the substrate, wherein the layer to be anodically oxidized is sandwiched between the insulating layers, and a projected pattern substantially parallel to the axis of the pore is formed on at least one of the insulating layers at positions between the pores.

Abstract translation: 可以控制通过阳极氧化形成具有孔的结构的方法，其结构，间距，位置，方向，形状等可以被控制。 该方法包括以下步骤：在基板上设置层压膜，层叠膜由绝缘层和要被阳极氧化并含有铝作为主要组成的层制成; 以及从所述层压膜的端面开始进行阳极氧化，以形成具有基本上平行于所述基板的表面的轴的多个孔，其中所述被阳极氧化的层被夹在所述绝缘层之间，并且基本上 在孔之间的位置处，在至少一个绝缘层上形成平行于孔的轴线。