公开(公告)号：US06500566B1

公开(公告)日：2002-12-31

申请号：US09659889

申请日：2000-09-12

Applicant: Gordon Smith

Inventor： Gordon Smith

IPC: B32B3104

CPC classification number: B32B15/08 ,  B32B7/06 ,  B32B7/12 ,  B32B2307/202 ,  B32B2457/08 ,  H05K3/025 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2203/0769 ,  H05K2203/0786 ,  Y10S428/901 ,  Y10T428/12556 ,  Y10T428/12569 ,  Y10T428/265 ,  Y10T428/2804 ,  Y10T428/2839 ,  Y10T428/31678 ,  Y10T428/31692

Abstract: A method for making a metal-clad laminate product including: providing a carrier film; depositing directly onto the carrier film a release agent layer, the release agent layer comprising an aqueous soluble polymer; forming a conductive metal layer on the release agent layer, the metal layer having a thickness of less than about 10,000 Angstroms; bonding the metal layer to a circuit board laminate layer; and removing the carrier film from the metal layer by peeling the carrier layer from the release agent layer.

Abstract translation: 一种制造覆金属层压制品的方法，包括：提供载体膜; 在载体膜上直接沉积脱模剂层，脱模剂层包含水溶性聚合物; 在所述脱模剂层上形成导电金属层，所述金属层的厚度小于约10,000埃; 将金属层粘合到电路板层压层上; 以及通过从载体层剥离脱模剂层而从金属层除去载体膜。

公开(公告)号：US06487048B1

公开(公告)日：2002-11-26

申请号：US09618201

申请日：2000-07-18

Applicant: George Anthony Dunn

Inventor： George Anthony Dunn

IPC: G11B5596

CPC classification number: G11B5/486 ,  G11B5/484 ,  H05K1/0218 ,  H05K1/0393 ,  H05K3/281 ,  H05K2201/0317 ,  H05K2201/0715

Abstract: A flexible cable consists of trace conductors disposed on a first flexible insulating substrate, and a second flexible insulating upper substrate. Holes are placed on one of the substrates to expose the central conductor. The cable is then washed and sputter deposited with a thin gold film of a thickness of about 10 angstroms. Finally, an aluminum layer of thickness of more than 100 angstroms is sputtered over the cable. The aluminum sputter layer is connected to the central conductor and then they are both electrically grounded. A cost-effective method of making such cable to solve the adhesion problem of the aluminum coating in the prior art.

Abstract translation: 柔性电缆由设置在第一柔性绝缘基板上的迹线导体和第二柔性绝缘上基板组成。 将孔放置在一个基板上以暴露中心导体。 然后将电缆清洗并溅射沉积厚度为约10埃的薄金膜。 最后，厚度超过100埃的铝层溅射在电缆上。 铝溅射层连接到中心导体，然后它们都是电接地的。 制造这种电缆以解决现有技术中的铝涂层的粘合问题的成本有效的方法。

公开(公告)号：US20020171530A1

公开(公告)日：2002-11-21

申请号：US10113621

申请日：2002-03-28

Applicant: VICTOR COMPANY OF JAPAN, LIMITED

Inventor： Motoshi Shindoh ,  Shigeru Michiwaki ,  Koichi Kamiyama ,  Hisanori Yoshimizu

IPC: H01F005/00

CPC classification number: H05K1/162 ,  H01C17/12 ,  H05K1/0206 ,  H05K1/165 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0361

Abstract: The present invention provides a thin film capacitance element having minimal deviation of capacitance value in a high accuracy formed on a printed circuit board (core material). The thin film capacitance element formed on a printed circuit board is composed of a lower electrode layer formed on the printed circuit board through an insulation layer, a dielectric layer formed on the lower electrode layer, an upper electrode layer formed on the dielectric layer and an electric pad for leading out the lower electrode layer, wherein the lower electrode layer is longer than the upper electrode layer in the horizontal direction and connected to the electric pad for leading out the lower electrode layer outside, and wherein the top surface of the upper electrode layer and the top surface of the electric pad for leading out the lower electrode layer are formed substantially in the same height.

Abstract translation: 本发明提供一种在印刷电路板（芯材）上形成的高精度的电容值偏差最小的薄膜电容元件。 形成在印刷电路板上的薄膜电容元件由通过绝缘层形成在印刷电路板上的下电极层，形成在下电极层上的电介质层，形成在电介质层上的上电极层和 用于引出下电极层的电焊盘，其中下电极层在水平方向上比上电极层长，并且连接到用于将下电极层引出外部的电焊盘，并且其中上电极的顶表面 并且用于引出下电极层的电焊盘的顶表面基本上形成为相同的高度。

公开(公告)号：US20020145845A1

公开(公告)日：2002-10-10

申请号：US09733815

申请日：2001-03-30

Applicant: MicroCoating Technologies of

Inventor： Andrew T. Hunt ,  Tzyy Jiuan Hwang ,  Helmut G. Hornis ,  Wen-Yi Lin

IPC: H01G004/005

CPC classification number: H05K1/162 ,  H01G4/085 ,  H05K3/388 ,  H05K3/467 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309

Abstract: Thin layer capacitors are formed from a first flexible metal layer, a dielectric layer between about 0.03 and about 2 microns deposited thereon, and a second flexible metal layer deposited on the dielectric layer. The first flexible metal layer may either be a metal foil, such as a copper, aluminum, or nickel foil, or a metal layer deposited on a polymeric support sheet. Depositions of the layers is by or is facilitate by combustion chemical vapor deposition or controlled atmosphere chemical vapor deposition.

Abstract translation: 薄层电容器由第一柔性金属层，沉积在其上的约0.03和约2微米之间的电介质层和沉积在电介质层上的第二柔性金属层形成。 第一柔性金属层可以是金属箔，例如铜，铝或镍箔，或者沉积在聚合物支撑片上的金属层。 通过燃烧化学气相沉积或受控气氛化学气相沉积，这些层的沉积是或通过其促进的。

公开(公告)号：US06462950B1

公开(公告)日：2002-10-08

申请号：US09725643

申请日：2000-11-29

Applicant: Helena Pohjonen

Inventor： Helena Pohjonen

IPC: H05K720

CPC classification number: H05K1/0207 ,  H01L23/3677 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0206 ,  H05K1/141 ,  H05K1/16 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/0317 ,  H05K2201/09563 ,  H01L2924/00

Abstract: Stacked substrates using passive integration components formed in silicon or stainless steel substrates interconnect with active elements mounted on the surface of the substrate to form a miniaturized power amplification module. Metal filled vias pass through the layers and carry electrical signals to and from the active elements and passive components. The metal filled vias function as thermal transfer heat sinks to transfer heat away from the active elements and the module.

公开(公告)号：US20020131254A1

公开(公告)日：2002-09-19

申请号：US10090933

申请日：2002-03-05

Inventor： Leonard W. Schaper

IPC: H05K007/02 ,  H05K007/06 ,  H05K007/10

CPC classification number: H05K1/0233 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/0393 ,  H05K1/141 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09672 ,  H05K2201/10515 ,  H05K2201/10689

Abstract: Surface applied passive devices for use on electronic circuit boards are formed by applying layers of conductive, insulating, and other material to a thin polymer film carrier. The surface applied passives are thin enough to fit underneath standard integrated circuit packages in order to conserve space on the circuit board. Resistors, capacitors, inductors and other passive circuits may be formed on thin polymer films, less than 8 mils thick. This significantly aids in conserving space on an electronic circuit board.

Abstract translation: 用于电子电路板的表面施加无源器件通过将导电，绝缘和其它材料层施加到薄聚合物膜载体上而形成。 表面施加的无源器件足够薄以适合标准集成电路封装，以节省电路板上的空间。 可以在小于8密耳厚的薄聚合物膜上形成电阻器，电容器，电感器和其它无源电路。 这有助于节省电子电路板上的空间。

公开(公告)号：US06444920B1

公开(公告)日：2002-09-03

申请号：US09491628

申请日：2000-01-26

Applicant: Mareike K. Klee ,  Hans-Wolfgang Brand ,  Uwe Mackens ,  Rainer Kiewitt ,  Antonius J. M. Nellisen ,  Antal F. J. Baggerman ,  Martin Fleuster ,  Marc De Samber

Inventor： Mareike K. Klee ,  Hans-Wolfgang Brand ,  Uwe Mackens ,  Rainer Kiewitt ,  Antonius J. M. Nellisen ,  Antal F. J. Baggerman ,  Martin Fleuster ,  Marc De Samber

IPC: H05K116

CPC classification number: H01L27/016 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/3442 ,  H05K3/368 ,  H05K3/403 ,  H05K2201/0317 ,  H01L2924/00

Abstract: The invention relates to a thin film circuit with component. The thin film circuit comprises a network of capacitors, or a network of capacitors and resistors, or a network of capacitors, resistors and inductances, or a network of capacitors and inductances. Current supply contacts such as, for example, SMD end contacts or bump end contacts render it possible for the thin film circuit to be connected to further components of a circuit or, for example, to be combined with active components through the use of contact surfaces.

Abstract translation: 本发明涉及一种具有部件的薄膜电路。 薄膜电路包括电容器网络或电容器和电阻器的网络，或电容器，电阻器和电感器的网络，或电容器和电感器的网络。 电流供应触点，例如SMD端触点或凸起端触点使得薄膜电路可以连接到电路的其它部件，或者例如通过使用接触表面与有源部件组合 。

公开(公告)号：US06440318B1

公开(公告)日：2002-08-27

申请号：US09507579

申请日：2000-02-18

Applicant: Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

Inventor： Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

IPC: H01B1300

CPC classification number: H05K1/167 ,  H05K3/0023 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09845 ,  H05K2201/10045 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A thin-film metal resistor (44) suitable for a multilayer printed circuit board (12), and a method for its fabrication. The resistor (44) generally has a multilayer construction, with the individual layers (34, 38) of the resistor (44) being self-aligned with each other so that a negative mutual inductance is produced that very nearly cancels out the self-inductance of each resistor layer (34, 38). As a result, the resistor (44) has a very low net parasitic inductance. In addition, the multilayer construction of the resistor (44) reduces the area of the circuit board (12) required to accommodate the resistor (44), and as a result reduces the problem of parasitic interactions with other circuit elements on other layers of the circuit board (12).

Abstract translation: 适用于多层印刷电路板（12）的薄膜金属电阻（44）及其制造方法。 电阻器（44）通常具有多层结构，其中电阻器（44）的各个层（34,38）彼此自对准，使得产生负的互感，其几乎抵消了自感 的每个电阻层（34,38）。 结果，电阻器（44）具有非常低的净寄生电感。 此外，电阻器（44）的多层结构减小了容纳电阻器（44）所需的电路板（12）的面积，结果减少了与其他层上的其它电路元件的寄生相互作用的问题 电路板（12）。

公开(公告)号：US06426146B1

公开(公告)日：2002-07-30

申请号：US09501442

申请日：2000-02-10

Applicant: Thomas J. Ameen ,  Edward Czapor

Inventor： Thomas J. Ameen ,  Edward Czapor

IPC: B32B1508

CPC classification number: C25D3/22 ,  C23C26/00 ,  C23C28/00 ,  C25D11/38 ,  H05K3/244 ,  H05K3/384 ,  H05K3/389 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/0723 ,  Y10T428/12028 ,  Y10T428/12438 ,  Y10T428/28 ,  Y10T428/2804 ,  Y10T428/31511 ,  Y10T428/31663

Abstract: This invention relates to a treated copper foil, comprising: a copper foil with a layer of zinc oxide adhered to the base surface of at least on side of said copper foil, said layer of zinc oxide having a thickness of about 3 Å to about 80 Å; and a layer of a trivalent chromium oxide adhered to said layer of zinc oxide. In one embodiment, the foil has a layer of a silane coupling agent adhered to the layer of trivalent chromium oxide. The invention also relates to a process for applying the layer of zinc oxide and the layer of trivalent chromium oxide to the copper foil. The invention also relates to laminates comprising a dielectric substrate and the foregoing copper foil adhered to the substrate. In one embodiment, the dielectric substrate is comprised of an epoxy resin made with a curing agent that is other than an amine curing agent.

Abstract translation: 本发明涉及一种经处理的铜箔，其特征在于包括：具有附着在所述铜箔的至少一侧的基底表面上的氧化锌层的铜箔，所述氧化锌层的厚度为约至约80 一个; 以及附着在所述氧化锌层上的三价铬氧化物层。 在一个实施方案中，箔具有粘附到三价铬氧化物层的硅烷偶联剂层。 本发明还涉及将氧化锌层和三价铬氧化物层施加到铜箔的方法。 本发明还涉及包括电介质基底和粘附到基底上的前述铜箔的层压体。 在一个实施例中，电介质基板由除了胺固化剂之外的固化剂制成的环氧树脂组成。

公开(公告)号：US06396387B1

公开(公告)日：2002-05-28

申请号：US09291259

申请日：1999-04-13

Applicant: Andrew T. Hunt ,  Wen-Yi Lin ,  Shara S. Shoup

Inventor： Andrew T. Hunt ,  Wen-Yi Lin ,  Shara S. Shoup

IPC: H01C1012

CPC classification number: H01L28/20 ,  C23C16/40 ,  C23C16/453 ,  H01C7/006 ,  H01C17/20 ,  H01C17/2416 ,  H05K1/167 ,  H05K3/064 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/0338 ,  H05K2203/1338

Abstract: In thin layer resistors comprising a patch of a layer of resistive material on an insulating substrate and means at spaced apart locations on the patch, the resistive material is formed of 95 to 99.5 wt % of a zero valence metal and between 5 and 0.5 wt % of a dielectric material.

Abstract translation: 在薄层电阻器中，包括在绝缘衬底上的电阻材料层的贴片和在贴片上的间隔开位置的装置，电阻材料由零价金属的95至99.5重量％和5至0.5重量％ 的介电材料。