公开(公告)号：US20050263905A1

公开(公告)日：2005-12-01

申请号：US11138932

申请日：2005-05-25

Applicant: Ryosuke Usul ,  Hideki Mizuhara ,  Yusuke Igarashi ,  Nobuhisa Takakusaki ,  Hayato Abe ,  Takeshi Nakamura

Inventor： Ryosuke Usul ,  Hideki Mizuhara ,  Yusuke Igarashi ,  Nobuhisa Takakusaki ,  Hayato Abe ,  Takeshi Nakamura

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H05K1/02 ,  H05K1/05 ,  H05K3/00 ,  H05K3/28 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L21/486 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L24/73 ,  H01L24/97 ,  H01L25/16 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/0035 ,  H05K3/284 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4647 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.

Abstract translation: 本发明提供一种适于通过绝缘层将多层叠布线层彼此连接的电路装置的制造方法。 在本发明的混合集成电路器件的制造方法中，通过在第一绝缘层上层叠第一导电膜，对第一导电膜进行构图来形成第一绞合层。 在第一布线层中，形成沿厚度方向突出的第一连接部。 此外，包括第一连接部的第一布线层被第二绝缘层覆盖。 第二绝缘层由第一树脂膜和第二树脂膜形成。 第二树脂膜比第一树脂膜含有更少的无机填料。 因此，具有可以容易地形成通孔的优点。

公开(公告)号：US20050258551A1

公开(公告)日：2005-11-24

申请号：US11041958

申请日：2005-01-26

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L21/44 ,  H01L21/60 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H05K1/11 ,  H05K3/00 ,  H05K3/24 ,  H05K3/28

CPC classification number: H01L24/85 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K1/111 ,  H05K3/002 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/09881 ,  H05K2201/10689 ,  H05K2203/049 ,  H05K2203/0594 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A packaging substrate used in a fine-pitch packaging comprises a circuit board, a plurality of packaging pads, an isolation pattern, and a conductive plating layer. The bonding pads are formed on an upper surface of the circuit board for electrically connecting to respective die pads. The isolation pattern filling the space between the neighboring bonding pads can cover all the exposed surfaces of the circuit board. A portion of the isolation pattern adjacent to the bonding pads has a same or a smaller thickness with respect to the bonding pads, and an upper surface and a portion of the sidewall of the packaging pads are thus exposed. The conductive plating layer covering the upper surface and the exposed sidewall of the packaging pads can extend outward from the sidewall to result an increased connectable area.

Abstract translation: 用于精细间距封装的封装衬底包括电路板，多个封装垫，隔离图案和导电镀层。 接合焊盘形成在电路板的上表面上，用于电连接到相应的管芯焊盘。 填充相邻接合焊盘之间的空间的隔离图案可以覆盖电路板的所有暴露表面。 与接合焊盘相邻的隔离图案的一部分相对于接合焊盘具有相同或更小的厚度，因此包装垫的侧壁的上表面和一部分被暴露。 覆盖包装垫的上表面和暴露的侧壁的导电镀层可以从侧壁向外延伸以导致增加的可连接区域。

公开(公告)号：US20050183883A1

公开(公告)日：2005-08-25

申请号：US10782640

申请日：2004-02-19

Applicant: Karl Bois ,  Timothy Michalka

Inventor： Karl Bois ,  Timothy Michalka

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K3/4688 ,  H05K1/024 ,  H05K2201/015 ,  H05K2201/0195 ,  H05K2201/0715 ,  H05K2201/09672 ,  H05K2201/09881 ,  Y10T29/49124

Abstract: A printed circuit board (PCB) substrate and method for construction of the same. In one embodiment, a first dielectric material is associated with a first current return layer and a second dielectric material is associated with a second current return layer. A signal path layer is interposed between the first dielectric material and the second dielectric material. An adhesive layer is interposed between the first dielectric material and the second dielectric material such that the adhesive layer is substantially coplanar relative to the signal path layer.

Abstract translation: 印刷电路板（PCB）基板及其构造方法。 在一个实施例中，第一电介质材料与第一电​​流返回层相关联，并且第二电介质材料与第二电流返回层相关联。 信号通路层介于第一电介质材料和第二电介质材料之间。 粘合剂层介于第一电介质材料和第二电介质材料之间，使得粘合剂层相对于信号路径层基本上是共面的。

公开(公告)号：US20050176177A1

公开(公告)日：2005-08-11

申请号：US10503804

申请日：2005-04-18

Applicant: Ron Zohar ,  Jacob Mozel ,  Ran Vilk

Inventor： Ron Zohar ,  Jacob Mozel ,  Ran Vilk

IPC: C08F2/48 ,  H05K3/00 ,  H05K3/28 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H05K3/0091 ,  H05K3/28 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/013 ,  H05K2203/081 ,  H05K2203/1509

Abstract: A method and apparatus for applying ink, according to a soldermask pattern, to a printed circuit board having elevated pads defining pad edges, the method including flooding the printed circuit board with ink such that the ink advances to the pad edges and is stopped thereby and thereat, without climbing onto the elevated pads.

Abstract translation: 一种用于根据焊接掩模图案将油墨施加到具有限定焊盘边缘的凸起焊盘的印刷电路板的方法和装置，所述方法包括用油墨浸渍印刷电路板，使得油墨前进到焊盘边缘并由此停止， 在那里，没有爬上升高的垫。

公开(公告)号：US20050140434A1

公开(公告)日：2005-06-30

申请号：US11010327

申请日：2004-12-14

Applicant: Toshiyuki Abe ,  Yoshihiro Suzuki ,  Masashi Katsumata

Inventor： Toshiyuki Abe ,  Yoshihiro Suzuki ,  Masashi Katsumata

IPC: H01L23/12 ,  H03F3/195 ,  H03F3/60 ,  H03G3/30 ,  H05K1/02 ,  H05K1/16 ,  H05K3/24 ,  H05K3/46 ,  H03F1/00

CPC classification number: H05K1/0265 ,  H01L2924/1423 ,  H03F3/195 ,  H03F2200/294 ,  H05K1/165 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0542

Abstract: An inductor element containing circuit board of the present invention comprises a plurality of conductive layers, and a conductor having an inductor function (inductor conductor segment) in one or more of the conductive layers, wherein at least part of the inductor conductor segment is made thicker than other conductors disposed within the circuit board. The at least part of the inductor conductor segment extends through an insulating layer disposed between the conductive layers, or is embedded in the insulating layer, wherein the part of the inductor conductor segment has a thickness one-half or more the thickness of the insulating layer. A power amplifier module of the present invention comprises the multi-layer circuit board, a semiconductor amplifier fabricated in the multi-layer circuit board, and an impedance matching circuit coupled to the output of the semiconductor amplifier. The impedance matching circuit has a portion thereof formed of the inductor conductor segment.

Abstract translation: 本发明的电感器元件电路板包括多个导电层，以及在一个或多个导电层中具有电感器功能（电感器导体段）的导体，其中电感器导体段的至少一部分变厚 而不是设置在电路板内的其它导线。 电感器导体段的至少一部分延伸穿过设置在导电层之间的绝缘层，或者嵌入在绝缘层中，其中电感器导体段的一部分具有绝缘层的厚度的一半或更多的厚度 。 本发明的功率放大器模块包括多层电路板，在多层电路板中制造的半导体放大器和耦合到半导体放大器的输出的阻抗匹配电路。 阻抗匹配电路具有由电感器导体段形成的部分。

公开(公告)号：US06898846B2

公开(公告)日：2005-05-31

申请号：US10224639

申请日：2002-08-21

Applicant: David Liu ,  Chengping Zhang ,  Michael T. Duignan

Inventor： David Liu ,  Chengping Zhang ,  Michael T. Duignan

IPC: H03H3/007 ,  H03H7/01 ,  H05K1/16 ,  H05K3/04 ,  H05K3/40 ,  H05K3/46 ,  H05K3/30

CPC classification number: H05K3/4614 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/06 ,  H03H7/1775 ,  H03H2001/0078 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/046 ,  H05K3/4069 ,  H05K3/4638 ,  H05K2201/0108 ,  H05K2201/09881 ,  H05K2201/09918 ,  H05K2201/10378 ,  H05K2203/0528 ,  H05K2203/107 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49165

Abstract: A method for manufacturing a modular electrical circuit includes the steps of pre-manufacturing a plurality of components having fine features such as resistors, capacitors, inductances, and conductors formed on a dielectric substrate. The pre-manufactured components are laminated each to the other in a predetermined order. Each pre-manufactured component includes one or more electrical elements of the same type coupled each to the other by conducting lines. Each dielectric substrate includes through vias filled with the conductive material which serve for cross-coupling of the elements of neighboring components. Position of the passive elements, as well as conductive lines and through vias, are pre-designed to allow precise coordination between the elements of different components in the multi-layered modular electrical circuit.

Abstract translation: 一种用于制造模块化电路的方法包括以下步骤：预先制造具有精细特征的部件，例如电阻器，电容器，电感和形成在电介质基片上的导体。 预先制造的部件按预定的顺序彼此分层。 每个预制的部件包括一个或多个相同类型的电气元件，每个通过导线彼此连接。 每个电介质基片包括填充有导电材料的通孔，其用于交叉耦合相邻元件的元件。 无源元件以及导线和通孔的位置被预先设计成允许多层模块化电路中的不同元件的元件之间的精确协调。

公开(公告)号：US20050081349A1

公开(公告)日：2005-04-21

申请号：US10739371

申请日：2003-12-17

Applicant: Ruei-Chih Chang

Inventor： Ruei-Chih Chang

IPC: H01L23/498 ,  H05K1/03 ,  H05K1/16 ,  H05K3/46 ,  H01L21/00

CPC classification number: H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0209 ,  H05K2201/09672 ,  H05K2201/09881 ,  Y10T29/435 ,  H01L2924/00

Abstract: An embedded capacitor structure in a circuit board and a method for fabricating the same are proposed. The circuit board is formed with a first circuit layer on at least one surface thereof, wherein the first circuit layer has at least one first electrode plate for the capacitor structure. Then, a dielectric layer is formed on the first circuit layer and made flush with the first circuit layer. The dielectric layer has a relatively low dielectric constant and good fluidity to effectively fill the spaces between patterned traces of the first circuit later. A capacitive material is deposited on the dielectric layer and the first circuit layer. Finally, a second circuit layer is formed on the capacitive material and has at least one second electrode plate corresponding to the first electrode plate, together with the capacitive material disposed in-between, to form the capacitor structure.

Abstract translation: 提出了一种电路板中的嵌入式电容器结构及其制造方法。 电路板在其至少一个表面上形成有第一电路层，其中第一电路层具有用于电容器结构的至少一个第一电极板。 然后，在第一电路层上形成电介质层并与第一电路层齐平。 介电层具有相对低的介电常数和良好的流动性，以有效地填充第一电路的图案化迹线之后的空间。 在电介质层和第一电路层上沉积电容材料。 最后，在电容材料上形成第二电路层，并且具有至少一个对应于第一电极板的第二电极板以及设置在其间的电容材料，以形成电容器结构。

公开(公告)号：US06866368B2

公开(公告)日：2005-03-15

申请号：US10400457

申请日：2003-03-28

Applicant: Yi-Jing Leu ,  Chih-Ching Chen ,  Ming-Chung Peng

Inventor： Yi-Jing Leu ,  Chih-Ching Chen ,  Ming-Chung Peng

IPC: B41J2/14 ,  B41J2/16 ,  H05K1/00 ,  H05K3/00 ,  H05K3/28 ,  H05K3/38 ,  H05K3/02 ,  H05K3/20 ,  H05K3/36

CPC classification number: B41J2/14 ,  B41J2/16 ,  B41J2/1623 ,  B41J2/1631 ,  B41J2/164 ,  B41J2002/14491 ,  H05K1/0393 ,  H05K3/0023 ,  H05K3/28 ,  H05K3/386 ,  H05K2201/09881 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49222 ,  Y10T29/49401

Abstract: A process of forming a flexible circuit board for ink jetting is provided. The process includes the steps of: providing an insulation tape; forming conductive traces on the insulation tape; and forming a photo-polymer layer filling between the conductive traces, wherein parts of the conductive traces are exposed to form a plurality of contacts. The material of the insulation tape can be polyimide, Teflon, polyamide, polymethylmethacrylate, polycarbonate, polyester, polyamide polyethylene-terephthalate copolymer, or any combination of the above materials. The material of the photo-polymer layer can be solder mask or polyimide.

Abstract translation: 提供了形成用于喷墨的柔性电路板的工艺。 该方法包括以下步骤：提供绝缘带; 在绝缘胶带上形成导电迹线; 以及形成填充在导电迹线之间的光聚合物层，其中部分导电迹线暴露以形成多个触点。 绝缘胶带的材料可以是聚酰亚胺，聚四氟乙烯，聚酰胺，聚甲基丙烯酸甲酯，聚碳酸酯，聚酯，聚酰胺聚对苯二甲酸乙二醇酯共聚物，或上述材料的任何组合。 光聚合物层的材料可以是焊接掩模或聚酰亚胺。

公开(公告)号：US06862189B2

公开(公告)日：2005-03-01

申请号：US09961172

申请日：2001-09-24

Applicant: Kazuhito Higuchi

Inventor： Kazuhito Higuchi

IPC: H01L21/98 ,  H05K3/20 ,  H05K3/46 ,  H05K7/10 ,  H05K7/12

CPC classification number: H05K3/4617 ,  H01L25/50 ,  H01L2224/83192 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H05K3/205 ,  H05K2201/0195 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2201/09963 ,  H05K2203/016 ,  H05K2203/1189

Abstract: An electronic component including an element main body section for performing an electrical function and a terminal section for electrically connecting the element main body section to a conductive member of an external device, the electronic component comprises a pair of sections arranged above the terminal section and opposite to each other in a stacking direction of the electronic component and a distance between the sections corresponding to a maximum thickness of the electronic component.

Abstract translation: 一种电子部件，包括用于执行电功能的元件主体部分和用于将元件主体部分电连接到外部装置的导电部件的端子部分，所述电子部件包括布置在所述端子部分上方的一对部分， 在电子部件的层叠方向上彼此相对的距离和对应于电子部件的最大厚度的部分之间的距离。

公开(公告)号：US20050019582A1

公开(公告)日：2005-01-27

申请号：US10920809

申请日：2004-08-18

Applicant: Kiyoshi Sato ,  Kazunori Kitamura

Inventor： Kiyoshi Sato ,  Kazunori Kitamura

IPC: C08F290/06 ,  C08F283/10 ,  C08G59/18 ,  C08G59/20 ,  C08L63/00 ,  C08L63/10 ,  H01L23/498 ,  H05K3/00 ,  H05K3/28 ,  H05K3/46 ,  B32B27/38 ,  B05D1/38

CPC classification number: H05K3/4626 ,  C08F283/10 ,  C08G59/18 ,  C08L63/10 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/28 ,  H05K3/4602 ,  H05K2201/0959 ,  H05K2201/09881 ,  Y10T428/31511 ,  Y10T428/31515 ,  C08L63/00 ,  H01L2924/00

Abstract: The thermosetting resin composition which is valuable for an undercoat of a printed wiring board, and does not leave an air bubble in a cured film, and makes the surface polishing easy and can form a smooth printed wiring board comprises (I) an adduct of epoxy resin with unsaturated aliphatic acid, (II) a (meth) acrylate, (III) a radical polymerization initiator, (IV) a crystallizable epoxy resin, and (V) a latent curing agent.

Abstract translation: 对印刷电路板的底涂层有价值且不在固化膜中留下气泡并使表面抛光容易并且可以形成光滑的印刷电路板的热固性树脂组合物包括（I）环氧树脂的加合物 具有不饱和脂肪酸的树脂，（II）（甲基）丙烯酸酯，（III）自由基聚合引发剂，（IV）可结晶环氧树脂和（V）潜伏性固化剂。