公开(公告)号：US20150076113A1

公开(公告)日：2015-03-19

申请号：US14481572

申请日：2014-09-09

Applicant: ASAHI GLASS COMPANY, LIMITED

Inventor： Kohei HORIUCHI

IPC: B44C1/22

CPC classification number: B44C1/228 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/54 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/0029 ,  H05K2201/09836 ,  H05K2201/10204 ,  H05K2203/163 ,  H01L2924/00

Abstract: A method including a) forming a through-hole in a dummy substrate including a surface by radiating a laser to the surface of the dummy substrate in a state where the dummy substrate is moved relative to the laser along a direction parallel to the surface of the dummy substrate, b) determining an angle α (−90°

Abstract translation: 一种方法，包括：在虚拟衬底相对于激光器沿着平行于所述虚拟衬底的表面的方向相对于激光器移动的状态下，通过在所述虚设衬底的表面辐射激光而在包括表面的虚设衬底中形成通孔 虚拟基板，b）确定通孔相对于垂直于虚设基板的表面的线的角度α（-90°<α<+ 90°），以及c）在绝缘基板中形成通孔 与步骤a）相同的条件，除了以角度＆bgr辐射激光; 相对于垂直于绝缘基板的表面的线。 角度＆bgr 被设定为相对于垂直于绝缘基板的表面的线的角度α线对称，并且满足＆bgr =α的关系。

公开(公告)号：US20150062850A1

公开(公告)日：2015-03-05

申请号：US14104632

申请日：2013-12-12

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Cheol Ho CHOI ,  Sung Jin Chun ,  Seok Kyu Lee ,  Dong Hoon Kim

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K1/185 ,  H05K3/4697 ,  H05K2201/10204

Abstract: Disclosed herein is a printed circuit board of a build-up structure in which an insulating layer and a circuit layer are stacked on a core layer, the core layer including: an electronic chip cavity in which an electronic chip is accommodated; and a dummy chip cavity in which a dummy chip is accommodated to offset warpage by the electronic chip.

Abstract translation: 本发明公开了一种堆积结构的印刷电路板，其中绝缘层和电路层堆叠在芯层上，芯层包括：容纳电子芯片的电子芯片腔; 以及虚拟芯片空腔，其中容纳虚拟芯片以抵消电子芯片的翘曲。

公开(公告)号：US20150010694A1

公开(公告)日：2015-01-08

申请号：US14316382

申请日：2014-06-26

Applicant: TAIYO YUDEN CO., LTD.

Inventor： Masashi MIYAZAKI ,  Yuichi SUGIYAMA ,  Tatsuro SAWATARI ,  Hideki YOKOTA ,  Yutaka HATA

IPC: H05K3/06 ,  H05K3/44

CPC classification number: H05K3/4697 ,  B05D3/12 ,  B05D5/12 ,  H05K1/185 ,  H05K3/0044 ,  H05K3/007 ,  H05K3/0094 ,  H05K3/04 ,  H05K3/06 ,  H05K3/30 ,  H05K3/42 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4647 ,  H05K2201/10204

Abstract: The method of manufacturing a substrate includes: forming a penetrating hole in a base layer; inserting a metal dummy part in the penetrating hole; forming an insulating portion made of synthetic resin to fill a ring-shaped gap between the penetrating hole and the dummy part; forming lower insulating layers, covering the bottom surface of the dummy part, that are made of synthetic resin on the bottom surface of the base layer to be continuous with the insulating portion; forming upper insulating layers, covering the top surface of the dummy part, that are made of synthetic resin on the top surface of the base layer to be continuous with the insulating portion; forming an exposing hole by routing in the upper insulating layers to expose the top surface of the dummy part; and forming a cavity by removing the dummy part exposed through the exposing hole by etching.

Abstract translation: 制造基板的方法包括：在基层中形成贯通孔; 将金属虚设部件插入穿透孔中; 形成由合成树脂制成的绝缘部分，以填充所述穿透孔和所述虚拟部件之间的环形间隙; 在所述基底层的底面上形成覆盖所述虚拟部的底面的由合成树脂制成的下绝缘层，以与所述绝缘部连续; 在所述基底层的顶表面上形成覆盖所述虚拟部分的上表面的由合成树脂制成的上绝缘层，以与所述绝缘部分连续; 通过在上绝缘层中布线来形成暴露孔以暴露虚拟部分的顶表面; 并且通过蚀刻去除暴露在暴露孔中的虚拟部分来形成空腔。

公开(公告)号：US20140215805A1

公开(公告)日：2014-08-07

申请号：US13757811

申请日：2013-02-03

Applicant: QUALCOMM INCORPORATED

Inventor： Yang ZHANG ,  Jack B. STEENSTRA

IPC: H05K13/00

CPC classification number: H05K13/00 ,  H05K1/0218 ,  H05K3/284 ,  H05K3/288 ,  H05K2201/10204 ,  H05K2201/10371 ,  H05K2203/0173 ,  Y10T29/49004

Abstract: A method for manufacturing a removable metalized conformal shield for a circuit substrate having at least one circuit component includes: forming a cast representing the circuit substrate having the at least one circuit component; preparing a metalized conformal shield using the cast; applying the metalized conformal shield to the circuit substrate; measuring an output of the circuit component of the circuit substrate; removing the metalized conformal shield from the circuit substrate; and adjusting the circuit component based on the measured output.

Abstract translation: 一种用于制造具有至少一个电路部件的电路基板的可拆卸金属化共形屏蔽的方法，包括：形成表示具有所述至少一个电路部件的电路基板的铸件; 使用铸件制备金属化保形盾; 将金属化的共形屏蔽施加到电路基板; 测量电路基板的电路部件的输出; 从电路基板去除金属化的共形屏蔽; 并且基于测量的输出来调整电路部件。

公开(公告)号：US08730677B2

公开(公告)日：2014-05-20

申请号：US13324770

申请日：2011-12-13

Applicant: Toni Wald ,  Sven Liborius

Inventor： Toni Wald ,  Sven Liborius

IPC: H05K7/20

CPC classification number: H05K1/0209 ,  H05K1/0207 ,  H05K3/341 ,  H05K2201/066 ,  H05K2201/10204

Abstract: The invention relates to a method of cooling electronic circuit boards using surface mounted devices (SMD), the method comprising the steps of: after or during the board layout, filling empty spaces V1, V2, V3, V4, V5, V6, V7, V8, V9, V10 with at a number of heat sink devices 1, 2, 3, 4, 5 near a thermal hot spot and connecting the number of heat sink devices 1, 2, 3, 4, 5 to a thermally conducting path 25, 27, 29, 31, 33, 35 of the board N, respectively. Further, the invention relates to a heat sink device 1, 2, 3, 4, 5 adapted to implement the method according to the invention.

Abstract translation: 本发明涉及使用表面贴装装置（SMD）冷却电子电路板的方法，该方法包括以下步骤：在电路板布局之后或期间填充空的空间V1，V2，V3，V4，V5，V6，V7， V8，V9，V10，其中多个散热装置1,2,3,4,5在热热点附近并将多个散热装置1,2,3,4,5连接到导热路径25 ，N号分别为27,29,31,33,35。 此外，本发明涉及适于实现根据本发明的方法的散热设备1,2,3,4,5。

公开(公告)号：US08508235B2

公开(公告)日：2013-08-13

申请号：US12958982

申请日：2010-12-02

Applicant: Swen Weitemeier ,  Christian Oldendorf

Inventor： Swen Weitemeier ,  Christian Oldendorf

IPC: H01H31/02

CPC classification number: G01R31/2815 ,  G01R31/2839 ,  G06F21/86 ,  H05K1/0275 ,  H05K2201/10151 ,  H05K2201/10204

Abstract: An electronic device, and associated method, provided with a circuit board (10), with a set of input contacts (IN/COM), a set of output contacts (OUT/COM) and an electrical circuit (18) connected between the input contacts (IN/COM) and the output contacts (OUT/COM) and a controller. The controller carries out a real-time test of the circuit board using a test signal introduced into the electrical circuit, the electrical circuit (18) being designed as a passive network having a characteristic transfer function and provided with at least one capacitive element, wherein the capacitive element is a conductor surface (221) forming a capacitor in the assembled state with a corresponding, device-side conductor surface (222″), which is connected to the electrical circuit (18) via a contact element in the assembled state, whereby the capacitive value of the capacitive element in the assembled state differs from the capacitive value of the capacitive element in the disassembled state.

Abstract translation: 一种具有电路板（10）的电子设备和相关方法，具有一组输入触点（IN / COM），一组输出触点（OUT / COM）和连接在输入端之间的电路（18） 触点（IN / COM）和输出触点（OUT / COM）和控制器。 控制器使用引入电路的测试信号对电路板进行实时测试，电路（18）被设计为具有特征传递函数并具有至少一个电容元件的无源网络，其中 电容性元件是在组装状态下形成电容器的导体表面（221），其中相应的器件侧导体表面（222“）经由组装状态的接触元件连接到电路（18） 由此，组装状态下的电容元件的电容值与分解状态下的电容元件的电容值不同。

公开(公告)号：US20130141873A1

公开(公告)日：2013-06-06

申请号：US13324770

申请日：2011-12-13

Applicant: Toni Wald ,  Sven Liborius

Inventor： Toni Wald ,  Sven Liborius

IPC: H05K7/20 ,  F28F7/00 ,  H05K3/10

CPC classification number: H05K1/0209 ,  H05K1/0207 ,  H05K3/341 ,  H05K2201/066 ,  H05K2201/10204

Abstract: The invention relates to a method of cooling electronic circuit boards using surface mounted devices (SMD), the method comprising the steps of: after or during the board layout, filling empty spaces V1, V2, V3, V4, V5, V6, V7, V8, V9, V10 with at a number of heat sink devices 1, 2, 3, 4, 5 near a thermal hot spot and connecting the number of heat sink devices 1, 2, 3, 4, 5 to a thermally conducting path 25, 27, 29, 31, 33, 35 of the board N, respectively. Further, the invention relates to a heat sink device 1, 2, 3, 4, 5 adapted to implement the method according to the invention.

Abstract translation: 本发明涉及使用表面贴装装置（SMD）冷却电子电路板的方法，该方法包括以下步骤：在电路板布局之后或期间填充空的空间V1，V2，V3，V4，V5，V6，V7， V8，V9，V10，其中多个散热装置1,2,3,4,5在热热点附近并将多个散热装置1,2,3,4,5连接到导热路径25 ，N号分别为27,29,31,33,35。 此外，本发明涉及适于实现根据本发明的方法的散热设备1,2,3,4,5。

公开(公告)号：US08420953B2

公开(公告)日：2013-04-16

申请号：US12941985

申请日：2010-11-08

Applicant: Meng-Che Yu

Inventor： Meng-Che Yu

IPC: H05K1/11

CPC classification number: H05K3/4015 ,  G11C29/24 ,  H05K1/141 ,  H05K3/4046 ,  H05K2201/10204 ,  H05K2201/10409 ,  H05K2203/162

Abstract: A dummy memory card includes a circuit board and a golden finger board. The circuit board includes a first conductive element and a second conductive element connected to a first electrical load. The golden finger board extends from the circuit board and is inserted into a memory slot of a motherboard. The golden finger board includes a first power pin and a first ground pin. The first conductive element is electrically connected to the first power pin. The second conductive element is electrically connected to the second power pin.

Abstract translation: 虚拟存储卡包括电路板和金手指板。 电路板包括连接到第一电负载的第一导电元件和第二导电元件。 金手指板从电路板延伸并插入主板的存储槽中。 金指板包括第一电源引脚和第一接地引脚。 第一导电元件电连接到第一电源引脚。 第二导电元件电连接到第二电源引脚。

公开(公告)号：US08102660B2

公开(公告)日：2012-01-24

申请号：US12343563

申请日：2008-12-24

Applicant: Mitsuhiko Sugane ,  Kazuya Nishida ,  Akira Okada

Inventor： Mitsuhiko Sugane ,  Kazuya Nishida ,  Akira Okada

IPC: H05K1/00

CPC classification number: H05K3/4691 ,  H05K1/0218 ,  H05K3/341 ,  H05K2201/0715 ,  H05K2201/10204 ,  Y10T29/49124

Abstract: There is provided a multi-layer printed wiring board that can perform impedance control, concurrently maintaining the flexibility of a flexible portion with one or more signal lines. Such a multi-layer printed wiring board includes a plurality of rigid board units; and a flexible board unit, connecting outer layers or inner layers of the plurality of rigid board units and extending over the outer layers or the inner layers of the plurality of rigid board units. The flexible board unit includes a signal layer sending signals between the plurality of rigid board units; ground layers sandwiching the signal layer; and intermediate layers each interposed between the signal layer and one of the ground layers.

Abstract translation: 提供了可以执行阻抗控制的多层印刷线路板，同时保持具有一个或多个信号线的柔性部分的柔性。 这种多层印刷线路板包括多个刚性板单元; 以及柔性板单元，连接所述多个刚性板单元的外层或内层，并且在所述多个刚性板单元的外层或内层上延伸。 柔性板单元包括在多个刚性板单元之间发送信号的信号层; 夹层信号层的接地层; 以及每个介于信号层和一个接地层之间的中间层。

公开(公告)号：US20110253788A1

公开(公告)日：2011-10-20

申请号：US13087562

申请日：2011-04-15

Applicant: Andrew Campbell ,  Brian Docherty ,  James Churchman ,  Kevin Maidment ,  Nick McGarvey

Inventor： Andrew Campbell ,  Brian Docherty ,  James Churchman ,  Kevin Maidment ,  Nick McGarvey

IPC: G06K7/06

CPC classification number: G06K7/0013 ,  G06K7/0008 ,  H05K1/0219 ,  H05K1/0275 ,  H05K2201/09263 ,  H05K2201/10204

Abstract: The present invention detects the current flowing through the contacts of the smart card reader due to the presence of a “shim”. Small value resistors are connected in series with either the Power connection or the Ground connection, or both. Values are typically 47 milliohms to 100 milliohms. The use of such small values ensures that little voltage is dropped across the resistors and that the card is therefore adequately powered. With no card present, the current through these resistors should be zero and therefore the voltage across the resistors will also be zero. Amplifier circuits are employed to monitor and amplify the voltage across the resistors and in the “PayPod” design the amplifier outputs are connected to analogue to digital inputs on the microprocessor. Where the microprocessor (or other processing electronics) used has no analogue to digital inputs, separate analogue to digital circuits may be used. The microprocessor may then monitor the current flowing into the power supply contacts of the card reader.

Abstract translation: 本发明由于存在“垫片”而检测流过智能卡读卡器的触头的电流。 小值电阻器与电源连接或接地连接或两者连接。 值通常为47毫欧至100毫欧。 使用这样小的值确保电阻器上的电压几乎没有下降，因此卡片被充分供电。 没有存在卡，通过这些电阻的电流应为零，因此电阻两端的电压也将为零。 采用放大器电路来监视和放大电阻两端的电压，而在“PayPod”设计中，放大器输出端连接到微处理器上的模拟数字输入端。 在使用微处理器（或其他处理电子设备）没有模数转换器的情况下，可以使用单独的模数转换电路。 然后，微处理器可以监测流入读卡器的电源触点的电流。