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公开(公告)号：US20240332267A1
公开(公告)日：2024-10-03
申请号：US18617086
申请日：2024-03-26
Inventor： Belgacem HABA , Cyprian Emeka UZOH , Rajesh KATKAR
IPC: H01L25/10 , H01L21/48 , H01L23/00 , H01L23/48 , H01L23/498 , H01L23/528
CPC classification number: H01L25/105 , H01L21/4857 , H01L23/481 , H01L23/49838 , H01L23/5286 , H01L24/08 , H01L2224/08145 , H01L2224/08225
Abstract: In some embodiments, a structure comprises an active element having a frontside and a backside opposite the frontside, the active element having active circuitry nearer the frontside than the backside and a power redistribution element having a frontside hybrid bonded to the backside of the active element, the power redistribution element comprising a first plurality of contact pads on the frontside of the power redistribution element and a second plurality of contact pads on a backside of the power redistribution element opposite the frontside of the power redistribution element, a pitch of the first plurality of contact pads is smaller than a pitch of the second plurality of contact pads, the power redistribution element configured to supply at least one of power and ground to the active element.
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公开(公告)号：US20240312951A1
公开(公告)日：2024-09-19
申请号：US18183768
申请日：2023-03-14
Inventor： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Gaius Gillman Fountain, JR. , Belgacem Haba , Rajesh Katkar
IPC: H01L23/00 , H01L21/027 , H01L21/56 , H01L23/12 , H01L25/16
CPC classification number: H01L24/80 , H01L21/0273 , H01L21/561 , H01L23/12 , H01L24/03 , H01L24/08 , H01L24/96 , H01L25/162 , H01L25/167 , H01L2224/0345 , H01L2224/03452 , H01L2224/03831 , H01L2224/03845 , H01L2224/08145 , H01L2224/80011 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2224/96 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043
Abstract: An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.
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公开(公告)号：US20240304593A1
公开(公告)日：2024-09-12
申请号：US18179126
申请日：2023-03-06
Inventor： Cyprian Emeka Uzoh
IPC: H01L23/00 , H01L25/00 , H01L25/065
CPC classification number: H01L24/80 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05647 , H01L2224/06181 , H01L2224/08145 , H01L2224/80009 , H01L2224/80013 , H01L2224/80357 , H01L2224/80379 , H01L2224/80895 , H01L2224/80896 , H01L2224/80906 , H01L2224/94 , H01L2224/97 , H01L2225/06565 , H01L2924/01006 , H01L2924/01014 , H01L2924/04642 , H01L2924/0504 , H01L2924/0544 , H01L2924/05494 , H01L2924/059
Abstract: Disclosed herein are processes and methods for direct bonding. In some embodiments, the process includes providing an element having a dielectric bonding surface and one or more conductive features exposed at the dielectric bonding surface, where the dielectric bonding surface has a planarity suitable for direct bonding. The process also includes, after providing the element, exposing the dielectric bonding surface to the products of a water vapor plasma prior to direct bonding the element.
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公开(公告)号：US20240298454A1
公开(公告)日：2024-09-05
申请号：US18590388
申请日：2024-02-28
Inventor： Belgacem HABA
IPC: H10B80/00 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC classification number: H10B80/00 , H01L24/08 , H01L24/80 , H01L25/0652 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/06562 , H01L2225/06582 , H01L2924/1431 , H01L2924/1436
Abstract: A bonded structure is disclosed. The bonded structure can include a carrier. The bonded structure can include a first memory unit disposed on the carrier having a first memory channel and a first plurality of memory dies directly hybrid bonded to one another. The bonded structure can also include a second memory unit having a second memory channel different from the first memory channel and a second plurality of memory dies directly hybrid bonded to one another. The second memory unit can be stacked on top of the first memory unit. The bonded structure can include a serializer-deserializer disposed in or on the carrier and electrically connected to the first and second memory channels of the first and second memory units. The serializer-deserializer can have an external channel configured to electrically connect the bonded structure to a processor.
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公开(公告)号：US12068278B2
公开(公告)日：2024-08-20
申请号：US18148369
申请日：2022-12-29
IPC: H01L23/00 , H01L21/02 , H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/683 , H01L21/78 , H01L23/31 , H01L25/00 , H01L25/065
CPC classification number: H01L24/83 , H01L21/02076 , H01L21/3085 , H01L21/31116 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3185 , H01L25/0657 , H01L25/50 , H01L21/3065 , H01L2221/68327 , H01L2221/68354 , H01L2221/68368 , H01L2224/83013 , H01L2224/83031 , H01L2224/83895 , H01L2224/83896
Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
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Patent Agency Ranking
公开(公告)号：US12046571B2
公开(公告)日：2024-07-23
申请号：US18058693
申请日：2022-11-23
Inventor： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Liang Wang , Rajesh Katkar , Guilian Gao , Laura Wills Mirkarimi
IPC: H01L23/00
CPC classification number: H01L24/26 , H01L24/03 , H01L24/09 , H01L24/27 , H01L24/30 , H01L24/83 , H01L2224/08257 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028
Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
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公开(公告)号：US20240234353A1
公开(公告)日：2024-07-11
申请号：US18451388
申请日：2023-08-17
Inventor： Belgacem Haba
IPC: H01L23/00 , H01L23/31 , H01L23/538 , H01L25/065
CPC classification number: H01L24/08 , H01L23/3121 , H01L23/5383 , H01L24/05 , H01L24/80 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L2224/05647 , H01L2224/08235
Abstract: A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.
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68.发明公开公开(公告)号：US20240222315A1
公开(公告)日：2024-07-04
申请号：US18148332
申请日：2022-12-29
Inventor： Cyprian Emeka Uzoh
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/94 , H01L2224/0345 , H01L2224/03614 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05166 , H01L2224/05184 , H01L2224/05186 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/08145 , H01L2224/8002 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/80906 , H01L2224/94 , H01L2924/04941
Abstract: An element, a bonded structure including the element, and a method of forming the same are disclosed. The bonded structure can include a first element having a first nonconductive field region and a first conductive feature. A surface of the first nonconductive field region and a surface of the first conductive feature at least partially defining a bonding surface of the first element. The first conductive feature includes a first portion and a second portion over the first portion and at least partially defines the surface of the first conductive feature. The first portion includes aluminum. The first conductive feature has a continuous sidewall along the first portion and the second portion. The second portion includes different metal composition from the first portion or comprising fluorine at the surface of the first conductive feature. The bonded structure can include a second element having a second nonconductive field region and a second conductive feature. A surface of the second nonconductive field region is directly bonded to the first nonconductive field region without an intervening adhesive along a bond interface and a surface of the second conductive feature is directly bonded to the second conductive feature without an intervening adhesive along the bond interface.
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69.发明公开公开(公告)号：US20240213191A1
公开(公告)日：2024-06-27
申请号：US18069910
申请日：2022-12-21
Inventor： Jeremy Alfred Theil , Cyprian Emeka Uzoh , Guilian Gao
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/08 , H01L24/80 , H01L2224/03462 , H01L2224/03616 , H01L2224/05147 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/3512
Abstract: Disclosed is an element including a conductive feature at a contact surface of the element and a nonconductive region at the contact surface in which the conductive feature is at least partially embedded. The contact feature includes a conductive material and an amount of impurities at a grain boundary of the conductive material. The impurities have a non-alloying material that does not form an alloy with the conductive material at a bonding temperature.
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70.发明公开公开(公告)号：US20240203948A1
公开(公告)日：2024-06-20
申请号：US18589231
申请日：2024-02-27
Inventor： Cyprian Emeka Uzoh , Rajesh Katkar , Thomas Workman , Guilian Gao , Gaius Gillman Fountain, JR. , Laura Wills Mirkarimi , Belgacem Haba , Gabriel Z. Guevara , Joy Watanabe
IPC: H01L25/065 , H01L21/56 , H01L23/00 , H01L23/31
CPC classification number: H01L25/0657 , H01L21/561 , H01L23/3121 , H01L24/97 , H01L2224/0401 , H01L2924/3511 , H01L2924/35121
Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
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