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    FLEXIBLE AND ADAPTABLE COMPUTING SYSTEM INFRASTRUCTURE
    61.
    发明申请
    FLEXIBLE AND ADAPTABLE COMPUTING SYSTEM INFRASTRUCTURE 审中-公开

    公开(公告)号：US20200214164A1

    公开(公告)日：2020-07-02

    申请号：US16499209

    申请日：2018-03-27

    Applicant: Cray Inc.

    Inventor： Wade Doll ,  Corey Knudsen ,  Dale Sand ,  Eric Lakin ,  Perry Franz ,  Paul Bonstrom ,  Rob Rongstad

    IPC: H05K7/14 ,  G06F1/28 ,  G06F1/26 ,  H05K7/20 ,  H04Q1/02

    Abstract: To achieve multiple benefits, a high speed computing system is configured in a hierarchical manner with flexibility and re-configurability concerns maximized. This begins with a particular cabinet architecture which is specifically designed to accommodate various needs and considerations. The cabinet or rack is designed to receive various chassis assemblies depending on the particular needs and or functions involved. These may include a compute chassis, a switch chassis, or a rectifier chassis, which can be incorporated into the cabinet. Within each chassis, specific components are then inserted, with each of these components being in a subsystem configuration. For example, the compute chassis is specifically designed to receive a number of compute blades. Similarly, the switch chassis is designed to receive a number of switch blades. Lastly, the rectifier chassis is configured to receive a number of rectifiers. Collectively, the multiple blades and chassis are all configured to cooperate with one another in an efficient manner. While various subassemblies are utilized, the cabinet or rack does accommodate certain centralized functions such as cooling and power distribution.

    System and method for dampening power swings in distributed computer environments
    62.
    发明授权
    System and method for dampening power swings in distributed computer environments 有权

    公开(公告)号：US10554519B2

    公开(公告)日：2020-02-04

    申请号：US15018823

    申请日：2016-02-08

    Applicant: Cray Inc.

    Inventor： Matthew Kappel ,  David Rush ,  Steve Martin ,  Jim Robanske

    IPC: H04L12/26

    Abstract: In a large scale computing system, a supervisory system is utilized to monitor the operations and requests of multiple components, and to manage such requests so that overall power considerations for the entire system are considered. The supervisory system has the ability to identify requests and aggregations of simultaneous requests that will create an adverse power effect, and to apply overall control methodologies which will help to minimize these adverse effects.

    DIRECT CONNECTION OF HIGH SPEED SIGNALS ON PCB CHIP
    63.
    发明申请
    DIRECT CONNECTION OF HIGH SPEED SIGNALS ON PCB CHIP 审中-公开

    公开(公告)号：US20200037448A1

    公开(公告)日：2020-01-30

    申请号：US16048267

    申请日：2018-07-28

    Applicant: Cray Inc.

    Inventor： Hyunjun Kim ,  Andy Becker ,  Jim Fitzke ,  Brad Smith ,  Paul Wildes

    IPC: H05K1/18 ,  H05K1/11 ,  H01B11/18 ,  H01R12/71

    Abstract: To eliminate signal loss and sources of signal attenuation, a connection methodology is utilized which enables high-speed signals to be directly communicated from particular integrated circuits housed on a printed circuit board, to other locations within a system. More specifically, a signal escape strategy directly connects a high-speed cable to a point on the circuit board which is very close to the integrated circuit itself. A back-side connection methodology is utilized so that electrical signals pass directly from the integrated circuit through a via, to a connection point on the backside of the circuit board. To accommodate this connection, a specially designed interposer and related paddle cards are utilized so the high-speed communication cable can be easily attached.

    APPLICATION RAMP RATE CONTROL IN LARGE INSTALLATIONS
    64.
    发明申请
    APPLICATION RAMP RATE CONTROL IN LARGE INSTALLATIONS 审中-公开

    公开(公告)号：US20190086987A1

    公开(公告)日：2019-03-21

    申请号：US16136218

    申请日：2018-09-19

    Applicant: Cray Inc.

    Inventor： Josh Williams ,  Steve Martin ,  Clark Snyder ,  David Rush ,  Matthew Kappel

    IPC: G06F1/32 ,  G06F9/50

    Abstract: To eliminate the adverse effects of power swings in a large scale computing system during the life cycle of an application or job, control of several operating characteristics for the collective group of processors is provided. By providing certain levels of coordination for the many processors utilized in large scale computing systems, significant and abrupt changes in power needs can be avoided. In certain circumstances, this may involve limiting the transition between several C-States of the processors involved and the overall power transitions for a large scale system are not detrimental and do not create issues for the data center or local power utility. Some cases will require stepped transitions between C-States, while other cases will include both stepped and modulated transitions. Other cases will incorporate random wait times at the various transitions in order to spread the power consumption involved. In yet further circumstances the C-States can be pinned to a specific setting, thus avoiding transitions caused by C-State transitions. To deal with further issues, the processor P-States can also be overridden.

    Transverse cooling system and method
    65.
    发明授权
    Transverse cooling system and method 有权

    公开(公告)号：US10034416B2

    公开(公告)日：2018-07-24

    申请号：US14887275

    申请日：2015-10-19

    Applicant: Cray Inc.

    Inventor： Gregory W. Pautsch ,  Eric D. Lakin

    IPC: H05K7/20

    Abstract: A system and method for cooling a plurality of electronics cabinets having horizontally positioned electronics assemblies. The system includes at least one blower configured to direct air horizontally across the electronics assemblies, and at least one intercooler configured to extract heat from the air flow such that the system is room neutral, meaning that the ambient temperature remains constant during operation of the system. A plurality of chassis backplanes and power supplies may also include an intercooler, wherein the intercoolers are electronically controlled such that the system is room neutral.

    High-bandwidth prefetcher for high-bandwidth memory
    66.
    发明授权
    High-bandwidth prefetcher for high-bandwidth memory 有权

    公开(公告)号：US09946654B2

    公开(公告)日：2018-04-17

    申请号：US15335041

    申请日：2016-10-26

    Applicant: Cray Inc.

    Inventor： Sanyam Mehta ,  James Robert Kohn ,  Daniel Jonathan Ernst ,  Heidi Lynn Poxon ,  Luiz DeRose

    IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/1045

    CPC classification number: G06F12/0862 ,  G06F12/1054 ,  G06F2212/602 ,  G06F2212/68

    Abstract: A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer (“ORB”). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.

    HIGH-BANDWIDTH PREFETCHER FOR HIGH-BANDWIDTH MEMORY
    67.
    发明申请
    HIGH-BANDWIDTH PREFETCHER FOR HIGH-BANDWIDTH MEMORY 有权

    公开(公告)号：US20180074963A1

    公开(公告)日：2018-03-15

    申请号：US15335041

    申请日：2016-10-26

    Applicant: Cray Inc.

    Inventor： Sanyam Mehta ,  James Robert Kohn ,  Daniel Jonathan Ernst ,  Heidi Lynn Poxon ,  Luiz DeRose

    IPC: G06F12/0862 ,  G06F12/1045

    CPC classification number: G06F12/0862 ,  G06F12/1054 ,  G06F2212/602 ,  G06F2212/68

    Abstract: A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer (“ORB”). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.

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