公开(公告)号：US20170372886A1

公开(公告)日：2017-12-28

申请号：US15426593

申请日：2017-02-07

Applicant: ASM IP Holding B.V.

Inventor： Shang Chen ,  Viljami Pore ,  Ryoko Yamada ,  Antti Juhani Niskanen

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/34 ,  C23C16/04

Abstract: Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment.

公开(公告)号：US20170133216A1

公开(公告)日：2017-05-11

申请号：US15414485

申请日：2017-01-24

Applicant: ASM IP HOLDING B.V.

Inventor： Antti J. Niskanen ,  Shang Chen ,  Viljami Pore ,  Atsuki Fukazawa ,  Hideaki Fukuda ,  Suvi P. Haukka

IPC: H01L21/02

CPC classification number: H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/823431

Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

公开(公告)号：US09564309B2

公开(公告)日：2017-02-07

申请号：US14167904

申请日：2014-01-29

Applicant: ASM IP HOLDING B.V.

Inventor： Antti J. Niskanen ,  Shang Chen ,  Viljami Pore ,  Atsuki Fukazawa ,  Hideaki Fukuda ,  Suvi P. Haukka

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/823431

Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

Abstract translation: 提供了通过原子层沉积（ALD）沉积氮化硅膜的方法和前体。 在一些实施方案中，硅前体包含碘配体。 当沉积到诸如FinFETS或其它类型的多栅极FET的三维结构上时，氮化硅膜可以具有相对均匀的垂直和水平部分的蚀刻速率。 在一些实施方案中，本公开的各种氮化硅膜具有小于具有稀释HF（0.5％）的热氧化物去除速率的一半的蚀刻速率。

公开(公告)号：US20160222515A1

公开(公告)日：2016-08-04

申请号：US15096511

申请日：2016-04-12

Applicant: ASM IP HOLDING B.V.

Inventor： Viljami Pore ,  Timo Hatanpää ,  Mikko Ritala ,  Markku Leskelä

IPC: C23C16/455 ,  H01L45/00 ,  H01L21/02 ,  C23C16/44 ,  C23C16/18

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/305 ,  C23C16/4408 ,  C23C16/45555 ,  H01L21/02521 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/0262 ,  H01L45/06 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1616

Abstract: Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, Sb—Te, Ge—Sb and Ge—Sb—Te thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR1R2R3)3 are preferably used, wherein R1, R2, and R3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.

Abstract translation: 提供了用于形成含有Sb，Sb-Te，Ge-Sb和Ge-Sb-Te薄膜的含VA薄膜的原子层沉积（ALD）工艺，以及相关组合物和结构。 优选使用Sb（SiR1R2R3）3的Sb前体，其中R1，R2和R3是烷基。 As，Bi和P前体也被描述。 还提供了用于合成这些Sb前体的方法。 还提供了在相变存储器件中使用Sb薄膜的方法。

公开(公告)号：US09401273B2

公开(公告)日：2016-07-26

申请号：US14566491

申请日：2014-12-10

Applicant: ASM IP HOLDING B.V.

Inventor： Viljami Pore

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02167 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/31111

Abstract: A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.

Abstract translation: 用于在衬底上沉积氮化硅膜的工艺可以包括多个完整的沉积循环，每个完整的沉积循环具有SiN子循环和SiCN子循环。 SiN子循环可以包括交替地和顺序地接触衬底与硅前体和SiN子循环氮前体。 SiCN子循环可以包括交替地和顺序地接触底物与含碳前体和SiCN亚循环氮前体。 SiN子循环和SiCN子循环可以包括原子层沉积（ALD）。 沉积氮化硅膜的工艺可以包括等离子体处理。 等离子体处理可以完成多个完整的沉积循环。

公开(公告)号：US20140273528A1

公开(公告)日：2014-09-18

申请号：US13830084

申请日：2013-03-14

Applicant: ASM IP HOLDING B.V.

Inventor： Antti J. Niskanen ,  Shang Chen ,  Viljami Pore

IPC: H01L21/02

CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/45553 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/66795

Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

Abstract translation: 提供了通过原子层沉积（ALD）沉积氮化硅膜的方法和前体。 在一些实施方案中，硅前体包含碘配体。 当沉积到诸如FinFETS或其它类型的多栅极FET的三维结构上时，氮化硅膜可以具有相对均匀的垂直和水平部分的蚀刻速率。 在一些实施方案中，本公开的各种氮化硅膜具有小于热稀释HF（0.5％）的热氧化物去除速率的一半的蚀刻速率。

公开(公告)号：US12211742B2

公开(公告)日：2025-01-28

申请号：US17467590

申请日：2021-09-07

Applicant: ASM IP Holding B.V.

Inventor： Timothee Blanquart ,  Viljami Pore ,  René Vervuurt ,  Jihee Jeon

IPC: C23C16/34 ,  C23C16/455 ,  C23C16/50 ,  C23C16/52 ,  H01L21/02 ,  H01L21/768

Abstract: Methods for manufacturing a structure comprising a substrate. The substrate comprises plurality of recesses. The recesses are at least partially filled with a gap filling fluid. The gap filling fluid comprises boron, nitrogen, and hydrogen. The gap filling fluid can be formed by introducing a precursor into the reaction chamber and introducing a co-reactant into the reaction chamber to form a gap filling fluid that at least partially fills the gap.

公开(公告)号：US12176243B2

公开(公告)日：2024-12-24

申请号：US18084789

申请日：2022-12-20

Applicant: ASM IP Holding B.V.

Inventor： Viljami Pore ,  Zecheng Liu

IPC: H01L21/762 ,  H01J37/32 ,  H01L21/67 ,  H01L29/06

Abstract: There is provided a method of filling one or more recesses by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, introducing a second reactant to the substrate with a second dose, wherein the first and the second doses overlap in an overlap area where the first and second reactants react and leave an initially substantially unreacted area where the first and the second areas do not overlap; introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant to form deposited material; and etching the deposited material. An apparatus for filling a recess is also disclosed.

公开(公告)号：US12107005B2

公开(公告)日：2024-10-01

申请号：US17491684

申请日：2021-10-01

Applicant: ASM IP Holding B.V.

Inventor： Zecheng Liu ,  Viljami Pore ,  Tommi Paavo Tynell ,  Yu Xu ,  Mikko Ruoho

IPC: H01L21/768 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01L21/76837 ,  H01J37/32146 ,  H01J37/32449 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/0228 ,  H01J2237/332

Abstract: The current disclosure relates to methods of depositing silicon-containing material on a substrate comprising a gap, wherein the method comprises providing the substrate in a reaction chamber and depositing a carbon-containing inhibition layer on the substrate, and depositing silicon-containing material on the substrate. Depositing the inhibition layer comprises supplying a carbon precursor comprising carbon in the reaction chamber and supplying first plasma in the reaction chamber to form a first reactive species from the carbon precursor for forming the inhibition layer on the substrate. The inhibition layer is deposited preferentially in the vicinity of the top of the gap. The disclosure further relates to methods of forming a structure, methods of manufacturing a device and to a semiconductor processing apparatus.

公开(公告)号：US12027365B2

公开(公告)日：2024-07-02

申请号：US17530983

申请日：2021-11-19

Applicant: ASM IP Holding B.V.

Inventor： Zecheng Liu ,  Sunja Kim ,  Viljami Pore ,  Jia Li Yao ,  Ranjit Borude ,  Bablu Mukherjee ,  René Henricus Jozef Vervuurt ,  Takayoshi Tsutsumi ,  Nobuyoshi Kobayashi ,  Masaru Hori

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/40 ,  C23C16/455 ,  H01J37/32 ,  H01L21/762

CPC classification number: H01L21/02315 ,  C23C16/0254 ,  C23C16/401 ,  C23C16/45536 ,  C23C16/45553 ,  H01J37/3244 ,  H01J37/32724 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76224 ,  H01J37/32082 ,  H01J2237/332

Abstract: Methods and related systems for filling a gap feature comprised in a substrate are disclosed. The methods comprise a step of providing a substrate comprising one or more gap features into a reaction chamber. The one or more gap features comprise an upper part comprising an upper surface and a lower part comprising a lower surface. The methods further comprise a step of subjecting the substrate to a plasma treatment. Thus, the upper surface is inhibited while leaving the lower surface substantially unaffected. Then, the methods comprise a step of selectively depositing a silicon-containing material on the lower surface.