公开(公告)号：US20060026400A1

公开(公告)日：2006-02-02

申请号：US11188311

申请日：2005-07-25

Applicant: Gerard Chauvel ,  Jean-Philippe Lesot ,  Gilbert Cabillic

Inventor： Gerard Chauvel ,  Jean-Philippe Lesot ,  Gilbert Cabillic

IPC: G06F9/00

CPC classification number: G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

Abstract: A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.

公开(公告)号：US20060026393A1

公开(公告)日：2006-02-02

申请号：US11186239

申请日：2005-07-21

Applicant: Gerard Chauvel ,  Maija Kuusela

Inventor： Gerard Chauvel ,  Maija Kuusela

IPC: G06F9/00

CPC classification number: G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

Abstract: In some embodiments, a processor comprises fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to software and partly in the hardware state machine.

Abstract translation: 在一些实施例中，处理器包括提取逻辑，其取指令，整数流水线以及与整数流水线分开并与整数流水线相互作用的硬件状态机。 该指令根据软件部分在整数流水线中执行，部分在硬件状态机中执行。

公开(公告)号：US06851072B2

公开(公告)日：2005-02-01

申请号：US09932378

申请日：2001-08-17

Applicant: Serge Lasserre ,  Gerard Chauvel

Inventor： Serge Lasserre ,  Gerard Chauvel

IPC: G06F1/20 ,  G06F1/32 ,  G06F9/312 ,  G06F9/50 ,  G06F11/07 ,  G06F11/20 ,  G06F11/34 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/30043 ,  G06F11/0715 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0292 ,  G06F12/0879 ,  G06F12/0891 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2212/1028 ,  G06F2212/681 ,  Y02D10/13 ,  Y02D10/24

Abstract: In accordance with a first embodiment of the invention, there is provided a method of operating a digital system that has a processor and a memory. A plurality of program tasks is executed on the processor (800). The processor requests access to memory in response to executing the tasks (802). Some of these access requests are not directly or not straightforwardly linked with the current program counter (PC); for example, a write transaction going through a write buffer (808). An access error resulting form this type of transaction error is referred to as an imprecise abort. A task-id value is supplied along with the address during a deferred memory access and corresponds to the task-id of the task that initiated the memory access (802). If an error condition that prevents normal completion of the memory transaction is detected (806), then a recovery routine uses the task-id value provided with the memory transaction request to identify which program task requested the transaction (810, 812). The recovery routine can then resolve the problem or kill the identified task.

Abstract translation: 根据本发明的第一实施例，提供了一种操作具有处理器和存储器的数字系统的方法。 在处理器（800）上执行多个程序任务。 响应于执行任务，处理器请求访问存储器（802）。 这些访问请求中的一些不直接或不直接与当前的程序计数器（PC）链接; 例如，通过写入缓冲器的写入事务（808）。 这种类型的事务错误导致的访问错误被称为不精确中止。 任务ID值与延迟存储器访问期间的地址一起提供，并且对应于启动存储器访问的任务的任务ID（802）。 如果检测到存储器事务的正常完成的错误条件（806），则恢复例程使用与存储器事务请求一起提供的task-id值来识别请求事务的程序任务（810,812）。 然后，恢复例程可以解决问题或者杀死已识别的任务。

公开(公告)号：US06839813B2

公开(公告)日：2005-01-04

申请号：US09932319

申请日：2001-08-17

Applicant: Gerard Chauvel

Inventor： Gerard Chauvel

IPC: G06F1/20 ,  G06F1/32 ,  G06F9/312 ,  G06F11/34 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1036 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/30047 ,  G06F11/3409 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2201/81 ,  G06F2201/815 ,  G06F2201/885 ,  G06F2212/1028 ,  G06F2212/656 ,  G06F2212/683 ,  Y02D10/13 ,  Y02D10/24

Abstract: A digital system and method of operation is provided in which several processing resources (340) and processors (350) are connected to a shared translation lookaside buffer (TLB) (300, 310(n)) of a memory management unit (MMU) and thereby access memory and devices. These resources can be instruction processors, coprocessors, DMA devices, etc. Each entry location in the TLB is filled a during the normal course of action by a set of translated address entries (308, 309) along with qualifier fields (301, 302, 303) that are incorporated with each entry. Operations can be performed on the TLB that are qualified by the various qualifier fields. A command (360) is sent by an MMU manager to the control circuitry of the TLB (320) during the course of operation. Commands are sent as needed to flush (invalidate), lock or unlock selected entries within the TLB. Each entry in the TLB is accessed (362, 368) and the qualifier field specified by the operation command is evaluated (364). This can be task ID field 302, resource ID field 301, shared indicator 303, or combinations of these. Operation commands can also specify a selected virtual address entry (305). Each TLB entry is modified in response to the command (366) only if its qualifier field(s) match the qualifier(s) specified by the operation command.

Abstract translation: 提供了一种数字系统和操作方法，其中多个处理资源（340）和处理器（350）连接到存储器管理单元（MMU）的共享转换后备缓冲器（TL，310,3N（n））和 从而访问内存和设备。 这些资源可以是指令处理器，协处理器，DMA设备等。TLB中的每个入口位置在正常操作过程中被一组翻译的地址条目（308,309）以及限定符字段（301,302， 303）。 可以在由各种限定词字段限定的TLB上执行操作。 在操作过程中，MMU管理器将命令（360）发送到TLB（320）的控制电路。 根据需要发送命令以刷新（无效），锁定或解锁TLB内的所选条目。 访问TLB中的每个条目（362,368），并且评估由操作命令指定的限定词字段（364）。 这可以是任务ID字段302，资源ID字段301，共享指示符303或这些的组合。 操作命令还可以指定所选择的虚拟地址条目（305）。 每个TLB条目只有在其限定符字段与操作命令指定的限定符匹配时才响应命令（366）进行修改。

公开(公告)号：US06697916B2

公开(公告)日：2004-02-24

申请号：US09932650

申请日：2001-08-17

Applicant: Serge Lasserre ,  Gerard Chauvel

Inventor： Serge Lasserre ,  Gerard Chauvel

IPC: G06F1206

CPC classification number: G06F9/30043 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F12/0292 ,  G06F12/0835 ,  G06F12/0862 ,  G06F12/0879 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/24

Abstract: A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block transfer circuitry (700, 702) is connected to the memory circuit and is operable to transfer a block of data (1650) to a selected portion of segments (1606) of the cache memory circuit. Fetch circuitry associated with the memory cache is operable to transfer data from a pre-selected region of the secondary memory (1650) to a particular segment of the plurality of segments and to assert a first valid bit corresponding to the segment when the miss detection circuitry (1610) detects a miss in the segment. Direct memory access (DMA) circuitry (1610) is connected to the memory cache for transferring data between the memory cache and a selectable region (1650) of a secondary memory. The cache can be operated in a first manner such that when a transfer request from the processor requests a first location in the cache memory that does not hold valid data, valid data is transferred (1652) from a pre-selected location in a secondary memory that corresponds directly to the first location. The cache can then be operated in a second manner such that data is transferred (1662) between the first location and a selectable location in the secondary memory, wherein the selected location need not directly correspond to the first location.

Abstract translation: 提供了一种数字系统和操作方法，其中数字系统具有至少一个具有相关联的多段高速缓冲存储器电路（506（n））的处理器，有效电路（VI）连接到存储器电路，并且可操作以 块传输电路（700,702）连接到存储器电路，并且可操作以将数据块（1650）传送到所述多个段的片段（1606）的选定部分 与存储器高速缓存相关联的获取电路可操作以将数据从辅助存储器（1650）的预先选择的区域传送到多个段的特定段，并且当对应于该段的第一有效位时 未命中检测电路（1610）检测该片段中的未命中，直接存储器访问（DMA）电路（1610）连接到存储器高速缓存，用于在存储器高速缓存和可选区域（1650）之间传送数据 第一记忆 高速缓存可以以第一方式操作，使得当来自处理器的传送请求请求高速缓冲存储器中不保存有效数据的第一位置时，有效数据从副存储器中的预先选择的位置传送（1652） 它直接对应于第一个位置。 然后可以以第二方式操作高速缓存，使得数据在辅助存储器中的第一位置和可选位置之间传送（1662），其中所选择的位置不需要直接对应于第一位置。

公开(公告)号：US06681297B2

公开(公告)日：2004-01-20

申请号：US09932222

申请日：2001-08-17

Applicant: Gerard Chauvel ,  Dominique D'Inverno ,  Serge Lasserre

Inventor： Gerard Chauvel ,  Dominique D'Inverno ,  Serge Lasserre

IPC: G06F1208

CPC classification number: G06F12/1027 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/30047 ,  G06F11/3409 ,  G06F12/0802 ,  G06F12/0842 ,  G06F12/0879 ,  G06F12/0891 ,  G06F2201/81 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/1028 ,  G06F2212/601 ,  G06F2212/681 ,  Y02D10/13 ,  Y02D10/16 ,  Y02D10/24 ,  Y02D10/34

Abstract: A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a level three (L3) physical memory. Each tag entry includes a task-ID qualifier field and a resource ID qualifier field. Data is loaded into various lines in the cache in response to cache access requests when a given cache access request misses. After loading data into the cache in response to a miss, a tag associated with the data line is set to a valid state. In addition to setting a tag to a valid state, qualifier values are stored in qualifier fields in the tag. Each qualifier value specifies a usage characteristic of data stored in an associated data line of the cache, such as a task ID. A miss counter (532) counts each miss and a monitoring task (1311) determines a miss rate for memory requests. If a selected miss rate threshold value is exceeded, the digital system is reconfigured in order to reduce the miss rate. The cache is reconfigured in response to an operation command (1314), such that each tag in the array of tags that contains a specified qualifier value is modified in accordance with the operation command. Other types of reconfiguration can be performed, such as remapping a selected program portion to operate in a different address range, locking a portion of the data entries within the cache, or defining addresses corresponding to a selected program task as uncacheable, for example.

Abstract translation: 数字系统具有数个处理器（1302），共享二级（L2）高速缓存（1300），具有每个条目具有相关标签的几个段以及三级（L3）物理存储器。 每个标签条目包括任务ID限定符字段和资源ID限定符字段。 当给定的高速缓存访​​问请求未命中时，响应于高速缓存访​​问请求，将数据加载到高速缓存中的各行中。 在将错误数据加载到缓存中之后，将与数据行相关联的标签设置为有效状态。 除了将标签设置为有效状态之外，限定符值存储在标签中的限定符字段中。 每个限定符值指定存储在高速缓存的关联数据行中的数据的使用特性，例如任务ID。 未命中计数器（532）计算每个未命中，并且监视任务（1311）确定存储器请求的未命中率。 如果超过选择的错失率阈值，则重新配置数字系统以减少错过率。 响应于操作命令（1314）重新配置高速缓存，使得根据操作命令修改包含指定的限定符值的标签阵列中的每个标签。 可以执行其他类型的重新配置，例如重新映射所选择的节目部分以在不同的地址范围内操作，将数据条目的一部分锁定在高速缓存内，或者将对应于所选择的节目任务的地址定义为不可缓存的。

公开(公告)号：US06678797B2

公开(公告)日：2004-01-13

申请号：US09932317

申请日：2001-08-17

Applicant: Gerard Chauvel ,  Serge Lasserre

Inventor： Gerard Chauvel ,  Serge Lasserre

IPC: G06F1208

CPC classification number: G06F12/0891 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/30043 ,  G06F12/0292 ,  G06F12/0862 ,  G06F12/0879 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/24

Abstract: A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment memory circuit. Validity circuitry is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block transfer circuitry is connected to the memory circuit and is operable to transfer a block of data to a selected portion of segments of the memory circuit such that a transfer to any segment within the selected portion of segments holding valid data is inhibited. A block transfer to a selected plurality of segments in the memory circuit is initiated (1600, 1624). During the block transfer, each segment is tested (1602) to detect if a segment within the selected plurality of segments holds valid data. A transfer within the block transfer to a segment is inhibited if the segment contains a valid data value (1604). Valid data can be transferred to a segment by a single data or instruction operation after a block transfer is initiated (1626). In this case, a transfer within the block transfer to the segment is inhibited if the segment contains a valid data value (1602).

Abstract translation: 提供了数字系统和操作方法，其中数字系统具有至少一个具有相关联的多段存储器电路的处理器。 有效电路连接到存储器电路，并且可操作以指示多个段中的每个段是否保存有效数据。 块传输电路连接到存储器电路，并且可操作以将数据块传送到存储器电路的段的选定部分，使得禁止对保持有效数据的段的所选部分内的任何段的传送。 开始向存储器电路中的选定的多个段的块传送（1600,1624）。 在块传输期间，测试每个段（1602）以检测所选择的多个段内的段是否保存有效数据。 如果段包含有效的数据值（1604），则块传输到段的传输被禁止。 在块传输启动后，有效数据可以通过单个数据或指令操作传送到段（1626）。 在这种情况下，如果段包含有效的数据值（1602），则在块传送到段内的传送被禁止。

公开(公告)号：US06621817B1

公开(公告)日：2003-09-16

申请号：US09348103

申请日：1999-07-06

Applicant: Gerard Chauvel

Inventor： Gerard Chauvel

IPC: H04L1228

CPC classification number: H04L49/3009 ,  H04L49/20

Abstract: A transport packet parser (42) includes a transport packet header decoder (50)for identifying a packet identifier (PID) and continuity counter (CC) associated with a current packet. The PID along with an enable (En) bit is input to an PID associative memory (52) in search mode to identify an address associated with the PID. The address is used to access a CC associated with a previous packet for the same PID in a random access memory (62). The previous continuity counter is used along with other header information to determine whether the current packets satisfies predetermined criteria. If so, the packet is passed to a transport packet buffer for further processing.

Abstract translation: 传输分组解析器（42）包括用于识别与当前分组相关联的分组标识符（PID）和连续性计数器（CC）的传输分组报头解码器（50）。 在搜索模式下，将PID与使能（En）位一起输入到PID关联存储器（52），以识别与PID相关联的地址。 地址用于在随机存取存储器（62）中访问与先前分组相关联的用于相同PID的CC。 先前的连续性计数器与其他报头信息一起使用以确定当前分组是否满足预定标准。 如果是这样，则将分组传递到传输分组缓冲器以进一步处理。

公开(公告)号：US06414726B1

公开(公告)日：2002-07-02

申请号：US08961958

申请日：1997-10-31

Applicant: Gerard Chauvel

Inventor： Gerard Chauvel

IPC: H04N5455

CPC classification number: H04N21/42653 ,  G09G5/14 ,  G09G5/395 ,  H04L29/06 ,  H04L69/22 ,  H04N5/4401 ,  H04N5/44508 ,  H04N19/42 ,  H04N19/61 ,  H04N21/426 ,  H04N21/42615 ,  H04N21/42623 ,  H04N21/431 ,  H04N21/434 ,  H04N21/439 ,  H04N21/44 ,  H04N21/443

Abstract: Circuitry for identifying digital data packets, each comprising a useful signal and a header signal containing data pertaining to the contents of the useful signal is provided. The circuitry includes a means (30) for extracting data from each header signal, which data is representative of a corresponding useful signal, a means for storing reference data in a memory, at addresses each corresponding to a packet type, and a means for comparing the data extracted from each header signal with said reference data stored in memory, and for the delivery, to a data processing unit (32,34), of an address signal indicating the nature of the corresponding packet. The data storage means and the comparison means preferably employ an associative memory (38) adapted to ensure the simultaneous comparison of the data extracted from each header signal with the reference data stored in memory.

Abstract translation: 提供了用于识别数字数据分组的电路，每个包括有用信号和包含与有用信号的内容有关的数据的报头信号。 该电路包括用于从每个标题信号中提取数据的装置（30），该数据表示对应的有用信号，用于将参考数据存储在存储器中的每个对应于分组类型的地址的装置和用于比较的装置 从具有存储在存储器中的所述参考数据的每个报头信号中提取的数据以及用于传送指示相应分组的性质的地址信号的数据处理单元（32,34）。 数据存储装置和比较装置优选地采用适于确保从每个报头信号提取的数据与存储在存储器中的参考数据同时进行比较的关联存储器（38）。

公开(公告)号：US06226291B1

公开(公告)日：2001-05-01

申请号：US08961764

申请日：1997-10-31

Applicant: Gerard Chauvel ,  Serge Lasserre ,  Mario Giani ,  Tiemen Spits

Inventor： Gerard Chauvel ,  Serge Lasserre ,  Mario Giani ,  Tiemen Spits

IPC: H04L1228

CPC classification number: H04N21/42653 ,  G09G5/14 ,  G09G5/395 ,  H04N5/44508 ,  H04N19/42 ,  H04N19/61 ,  H04N21/42615 ,  H04N21/42623 ,  H04N21/431 ,  H04N21/434 ,  H04N21/439 ,  H04N21/44 ,  H04N21/443

Abstract: A transport stream parser system is provided that utilizes an intermediate buffer for containing packets after processing with an associated flag and then use a processor for further processing of packets selected by such flags.

Abstract translation: 提供了一种传输流解析器系统，其利用中间缓冲器在用关联的标志处理之后包含分组，然后使用处理器来进一步处理由这样的标志选择的分组。