公开(公告)号：US20190220420A1

公开(公告)日：2019-07-18

申请号：US16328044

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Robert G. Blankenship ,  Raj K. Ramanujan

IPC: G06F12/14 ,  G06F12/0813 ,  G06F12/0815 ,  G06F9/50 ,  G06F12/0808

CPC classification number: G06F12/1425 ,  G06F9/50 ,  G06F9/5016 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0826 ,  G06F12/0831 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/154

Abstract: Examples may include techniques to enable cache coherency of objects in a distributed shared memory (DSM) system, even where multiple nodes in the system manage the objects. Node memory space includes a tracking address space (TAS) where lines in the TAS correspond to objects in the (DSM). Access to the objects and the TAS is managed by a host fabric interface (HFI) caching agent in HFI of a node.

公开(公告)号：US10268502B2

公开(公告)日：2019-04-23

申请号：US15637476

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Vadim Sukhomlinov ,  Roman Dementiev

IPC: G06F9/46 ,  G06F12/0831 ,  G06F9/30

Abstract: A method to perform atomic transactions in non-volatile memory (NVM) under hardware transactional memory is disclosed. The method includes tracking an order among transaction log entries that includes arranging transaction logs in an order that is based on when corresponding transactions were executed. Moreover, the method includes, using the ordered transaction logs to recover data states of the nonvolatile memory, by identifying a first unconfirmed transaction associated with a transaction completion uncertainty event based on a corresponding one of the transaction logs including a first commit marker but not including a confirm marker, undoing first ones of the transactions in reverse time order starting at a last transaction that recorded a second commit marker, up to and including the first unconfirmed transaction that recorded the first commit marker, and redoing second ones of the transactions in forward time order from a first confirmed transaction up to but not including the first unconfirmed transaction that recorded the first commit marker.

公开(公告)号：US20190104178A1

公开(公告)日：2019-04-04

申请号：US15721867

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Vadim Sukhomlinov ,  Kshitij A. Doshi ,  Edwin Verplanke

IPC: H04L29/08

Abstract: Disclosed embodiments relate to cloud scaling with non-blocking, non-spinning cross-domain event synchronization and data communication. In an example, a processor includes a memory to store multiple virtual hardware thread (VHTR) descriptors, each including an architectural state, a monitored address range, a priority, and an execution state, fetch circuitry to fetch instructions associated with a plurality of the multiple VNFs, decode circuitry to decode the fetched instructions, scheduling circuitry to allocate and pin a VHTR to each of the plurality of VNFs, schedule execution of a VHTR on each of a plurality of cores, set the execution state of the scheduled VHTR; and in response to a monitor instruction received from a given VHTR, pause the given VHTR and switch in another VHTR to use the core previously used by the given VHTR, and, upon detecting a store to the monitored address range, trigger execution of the given VHTR.

公开(公告)号：US20190042515A1

公开(公告)日：2019-02-07

申请号：US15848218

申请日：2017-12-20

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Da-Ming Chiang ,  Kshitij A. Doshi ,  Suraj Prabhakaran ,  Mark A. Schmisseur

IPC: G06F13/40 ,  G06F13/362 ,  G06N3/04 ,  G06F13/42 ,  G06F9/455

Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.

公开(公告)号：US20190042457A1

公开(公告)日：2019-02-07

申请号：US16109228

申请日：2018-08-22

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Bhanu Shankar ,  Vineet Singh

IPC: G06F12/0893

Abstract: Apparatuses, methods and storage medium associated with workload working set size determination, are disclosed herein. In embodiments, at least one computer-readable storage medium includes instructions stored therein to cause an apparatus to intermittently sample memory access operations associated with execution of a workload; generate a trace of memory addresses of the memory access operations sampled; generate a profile of average memory footprints for various trace window sizes; and generate a profile of cache miss rate. The profile of cache miss rate is used to determine a working set size of the workload. Other embodiments are also described and claimed.

公开(公告)号：US20190007284A1

公开(公告)日：2019-01-03

申请号：US15639465

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Francesc Guim Bernat ,  Mark A. Schmisseur

IPC: H04L12/26 ,  H04L29/08

Abstract: Technologies for producing proactive notifications of data storage performance include a compute device. The compute device is to obtain key indicator data indicative of a performance condition associated with operations of one or more data storage devices and an associated predefined threshold that, if satisfied, indicates the presence of a key indicator. The compute device is also to obtain remedial action data indicative of a remedial action to be performed by the compute device in response to identification of the key indicator in telemetry data produced by the compute device during operation, analyze the telemetry data to determine whether the key indicator is present in the telemetry data, perform, in response to a determination that the key indicator is present, the predefined remedial action, and send a notification of the predefined indicator to a remote compute device.

公开(公告)号：US20190004858A1

公开(公告)日：2019-01-03

申请号：US15636969

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan ,  Alejandro Duran Gonzalez ,  Harald Servat

IPC: G06F9/50 ,  H04W8/22

Abstract: Technologies for dynamically sharing remote resources include a computing node that sends a resource request for remote resources to a remote computing node in response to a determination that additional resources are required by the computing node. The computing node configures a mapping of a local address space of the computing node to the remote resources of the remote computing node in response to sending the resource request. In response to generating an access to the local address, the computing node identifies the remote computing node based on the local address with the mapping of the local address space to the remote resources of the remote computing node and performs a resource access operation with the remote computing node over a network fabric. The remote computing node may be identified with system address decoders of a caching agent and a host fabric interface. Other embodiments are described and claimed.

公开(公告)号：US09996361B2

公开(公告)日：2018-06-12

申请号：US14757609

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Asit K. Mishra ,  Kshitij A. Doshi ,  Elmoustapha Ould-Ahmed-Vall ,  Deborah T. Marr

IPC: G06F9/315 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3889 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30112 ,  G06F9/3861 ,  G06F9/3887

Abstract: A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.

公开(公告)号：US09952941B2

公开(公告)日：2018-04-24

申请号：US14916768

申请日：2013-12-19

Applicant: INTEL CORPORATION

Inventor： Kshitij A. Doshi ,  Rahul Khanna ,  Minh Tung Duy Le ,  Paul H. Dormitzer

IPC: G06F11/14 ,  G06F11/20

CPC classification number: G06F11/1471 ,  G06F11/2033 ,  G06F11/2035 ,  G06F11/2043 ,  G06F2201/805 ,  G06F2201/85

Abstract: Technologies for virtual multipath access include a computing device configured to sequester a recovery partition from a host partition while allowing the recovery partition to access one or more resources of the host partition such as host memory or data storage. A remote computing device determines whether the host partition is responsive. The recovery partition receives a request for host state data of the host partition from the remote computing device in response to a determination that the host partition is not responsive. The recovery partition retrieves the requested host state data using a host state index maintained by the host partition and transmits the requested host state data to the remote computing device. The host state index may identify the location of the requested host state data. The remote computing device may perform a recovery operation based on the received host state data. Other embodiments are described and claimed.

公开(公告)号：US20180097743A1

公开(公告)日：2018-04-05

申请号：US15283314

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Raj K. Ramanujan ,  Gaspar Mora Porta ,  Daniel Rivas Barragan

IPC: H04L12/911 ,  H04L29/08 ,  H04L12/26

CPC classification number: H04L43/08 ,  H04L12/185 ,  H04L41/12 ,  H04L47/15 ,  H04L47/823 ,  H04L67/2842 ,  H04L69/326

Abstract: Apparatus, methods, and system for implementing cluster-wide operational metrics access for coordinated agile scheduling. One embodiment of the apparatus includes a memory to store instructions; a processing circuitry to execute instructions; and an interface circuitry. The interface circuitry to provide metrics associated with the apparatus to one or more subscriber nodes or network components in a managed cluster and to subscribe, via a metrics subscription request, to receive from one or more publisher nodes or network components in the managed cluster, metrics associated with the one or more publisher nodes or network components. The metrics to be stored in a dedicated location of the memory. The provision and subscription of metrics may be made using new protocols added to Layer 4 or transport layer of a network communication model and/or over a dedicated communication channel. The dedicated communication channel may be of low bandwidth with fixed priority and deterministic latency.