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公开(公告)号:US20190266782A1
公开(公告)日:2019-08-29
申请号:US16411628
申请日:2019-05-14
Applicant: Imagination Technologies Limited
Inventor: John W. Howson , Steven J. Clohset , Ali Rabbani
Abstract: A ray tracing unit is implemented in a graphics rendering system. The ray tracing unit comprises: processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.
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公开(公告)号:US10366530B2
公开(公告)日:2019-07-30
申请号:US15793343
申请日:2017-10-25
Applicant: Imagination Technologies Limited
Inventor: Xile Yang , John W. Howson , Simon Fenney
Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
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公开(公告)号:US10332303B2
公开(公告)日:2019-06-25
申请号:US15138868
申请日:2016-04-26
Applicant: Imagination Technologies Limited
Inventor: John W. Howson , Steven J. Clohset , Ali Rabbani
Abstract: A ray tracing unit is implemented in a graphics rendering system. The ray tracing unit comprises: processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.
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公开(公告)号:US10249085B2
公开(公告)日:2019-04-02
申请号:US15259299
申请日:2016-09-08
Applicant: Imagination Technologies Limited
Inventor: John W. Howson , Xile Yang , Andrea Sansottera , Lorenzo Belli , Jonathan Redshaw
Abstract: When untransformed display lists are used in a tile-based graphics processing system, the processing involved in deriving sub-primitives may need to be performed in both the geometry processing phase and the rasterization phase. To reduce the duplication of this processing, the control stream data for a tile includes sub-primitive indications to indicate which sub-primitives are to be used for rendering a tile. This allows the sub-primitives to be determined efficiently in the rasterization phase based on this information determined in the geometry processing phase. Furthermore, a hierarchical cache system may be used to store a hierarchy of graphics data items used for deriving sub-primitives. If graphics data items for deriving a sub-primitive are stored in the cache, the retrieval of these graphics data items from the cache in the rasterization phase can reduce the amount of processing performed to derive the sub-primitives.
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公开(公告)号:US20190088002A1
公开(公告)日:2019-03-21
申请号:US15705976
申请日:2017-09-15
Applicant: Imagination Technologies Limited
Inventor: John W. Howson , Luke T. Peterson
CPC classification number: G06T15/06 , G06T15/005 , G06T15/20 , G06T15/30 , G06T15/40 , G06T15/60 , G06T17/005 , G06T2210/21
Abstract: Ray tracing units, processing modules and methods are described for generating one or more reduced acceleration structures to be used for intersection testing in a ray tracing system for processing a 3D scene. Nodes of the reduced acceleration structure(s) are determined, wherein a reduced acceleration structure represents a subset of the 3D scene. The reduced acceleration structure(s) are stored for use in intersection testing. Since the reduced acceleration structures represent a subset of the scene (rather than the whole scene) the memory usage for storing the acceleration structure is reduced, and the latency in the traversal of the acceleration structure is reduced.
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66.
公开(公告)号:US10210649B2
公开(公告)日:2019-02-19
申请号:US15259351
申请日:2016-09-08
Applicant: Imagination Technologies Limited
Inventor: Andrea Sansottera , John W. Howson , Xile Yang , Jonathan Redshaw
Abstract: When untransformed display lists are used in a tile-based graphics processing system, the processing involved in deriving sub-primitives may need to be performed in both the geometry processing phase and the rasterisation phase. To reduce the duplication of this processing, the control stream data for a tile includes sub-primitive indications to indicate which sub-primitives are to be used for rendering a tile. This allows the sub-primitives to be determined efficiently in the rasterisation phase based on this information determined in the geometry processing phase. Furthermore, a hierarchical cache system may be used to store a hierarchy of graphics data items used for deriving sub-primitives. If graphics data items for deriving a sub-primitive are stored in the cache, the retrieval of these graphics data items from the cache in the rasterisation phase can reduce the amount of processing performed to derive the sub-primitives.
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公开(公告)号:US20180268600A1
公开(公告)日:2018-09-20
申请号:US15985312
申请日:2018-05-21
Applicant: Imagination Technologies Limited
Inventor: John W. Howson , Luke T. Peterson
CPC classification number: G06T15/06 , G06T1/20 , G06T15/005
Abstract: Systems and methods of geometry processing, for rasterization and ray tracing processes provide for pre-processing of source geometry, such as by tessellating or other procedural modification of source geometry, to produce final geometry on which a rendering will be based. An acceleration structure (or portion thereof) for use during ray tracing is defined based on the final geometry. Only coarse-grained elements of the acceleration structure may be produced or retained, and a fine-grained structure within a particular coarse-grained element may be Produced in response to a collection of rays being ready for traversal within the coarse grained element. Final geometry can be recreated in response to demand from a rasterization engine, and from ray intersection units that require such geometry for intersection testing with primitives. Geometry at different resolutions can be generated to respond to demands from different rendering components.
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68.
公开(公告)号:US20180197270A1
公开(公告)日:2018-07-12
申请号:US15868368
申请日:2018-01-11
Applicant: Imagination Technologies Limited
Inventor: John W. Howson , Richard Broadhurst , Steven Fishwick
CPC classification number: G06T1/20 , G06F9/38 , G06T1/60 , G06T7/11 , G06T11/40 , G06T15/005 , H04N19/00 , H04N19/115 , H04N19/117 , H04N19/124 , H04N19/14 , H04N19/174
Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.
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公开(公告)号:US20180108174A1
公开(公告)日:2018-04-19
申请号:US15793343
申请日:2017-10-25
Applicant: Imagination Technologies Limited
Inventor: Xile Yang , John W. Howson , Simon Fenney
CPC classification number: G06T15/405 , G06T15/005
Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth threshold for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
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公开(公告)号:US20170161204A1
公开(公告)日:2017-06-08
申请号:US15367370
申请日:2016-12-02
Applicant: Imagination Technologies Limited
Inventor: Dave Roberts , Mario Sopena Novales , John W. Howson
IPC: G06F12/1009 , G06T1/60 , G06T1/20 , G06F9/455
CPC classification number: G06F12/1009 , G06F9/45558 , G06F13/16 , G06F2009/45583 , G06F2212/1024 , G06F2212/1052 , G06F2212/151 , G06F2212/152 , G06F2212/651 , G06F2212/657 , G06T1/20 , G06T1/60
Abstract: A method of GPU virtualization comprises allocating each virtual machine (or operating system running on a VM) an identifier by the hypervisor and then this identifier is used to tag every transaction deriving from a GPU workload operating within a given VM context (i.e. every GPU transaction on the system bus which interconnects the CPU, GPU and other peripherals). Additionally, dedicated portions of a memory resource (which may be GPU registers or RAM) are provided for each VM and whilst each VM can only see their allocated portion of the memory, a microprocessor within the GPU can see all of the memory. Access control is achieved using root memory management units which are configured by the hypervisor and which map guest physical addresses to actual memory addresses based on the identifier associated with the transaction.
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