公开(公告)号：US20240213201A1

公开(公告)日：2024-06-27

申请号：US18599147

申请日：2024-03-07

Applicant: Intel Corporation

Inventor： MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: H01L23/00 ,  G06F13/14 ,  G06F13/38 ,  G06F13/42 ,  H01L25/065

CPC classification number: H01L24/18 ,  G06F13/14 ,  G06F13/385 ,  G06F13/4221 ,  G06F13/4265 ,  H01L25/0652 ,  H01L25/0655

Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

公开(公告)号：US11929339B2

公开(公告)日：2024-03-12

申请号：US18300329

申请日：2023-04-13

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: G06F13/38 ,  G06F13/14 ,  G06F13/42 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/18 ,  G06F13/14 ,  G06F13/385 ,  G06F13/4221 ,  G06F13/4265 ,  H01L25/0652 ,  H01L25/0655

Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

公开(公告)号：US20230370068A1

公开(公告)日：2023-11-16

申请号：US18198122

申请日：2023-05-16

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H03K19/17736 ,  H03K19/17796 ,  H04L41/5019

CPC classification number: H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US20230198526A1

公开(公告)日：2023-06-22

申请号：US18169988

申请日：2023-02-16

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

IPC: H03K19/1776 ,  H01L25/18 ,  H01L23/367

CPC classification number: H03K19/1776 ,  H01L25/18 ,  H01L23/367 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06589

Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

公开(公告)号：US11658144B2

公开(公告)日：2023-05-23

申请号：US17466396

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: G06F13/14 ,  H01L23/00 ,  G06F13/38 ,  H01L25/065 ,  G06F13/42

CPC classification number: H01L24/18 ,  G06F13/14 ,  G06F13/385 ,  G06F13/4221 ,  G06F13/4265 ,  H01L25/0652 ,  H01L25/0655

Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

公开(公告)号：US11610856B2

公开(公告)日：2023-03-21

申请号：US16449923

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Robert Sankman ,  Dheeraj Subbareddy ,  Md Altaf Hossain ,  Ankireddy Nalamalpu

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

Abstract: An integrated circuit package may be formed comprising an interposer with a center die and a plurality of identical integrated circuit dice positioned around the center die and attached to the interposer, wherein the center die is the switch/router for the plurality of identical integrated circuit dice. The interposer comprises a substrate, a central pattern of bond pads formed in or on the substrate for attaching the center die, and substantially identical satellite patterns formed in or on the substrate for attaching identical integrated circuit dice. The central pattern of bond pads has repeating sets of a specific geometric pattern and wherein the identical satellite patterns of bond pads are positioned to form the same geometric pattern as the specific geometric pattern of the central pattern of bond pads. Thus, substantially identical conductive routes may be formed between the center die and each of the identical integrated circuit dice.

公开(公告)号：US11609262B2

公开(公告)日：2023-03-21

申请号：US16232023

申请日：2018-12-25

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Dhananjay Raghavan

IPC: G01R31/26 ,  G01R31/317 ,  G01R31/3193 ,  G01R31/28 ,  G01R31/30 ,  G01R31/3185

Abstract: An integrated circuit die includes a core fabric configurable to include an aging measurement circuit and a device manager coupled to the core fabric to operate the aging measurement circuit for a select period of time. The aging measurement circuit includes a counter to count transitions of a signal propagating through the aging measurement circuit during the select period of time when the aging measurement circuit is operating. The transitions of the signal counted by the counter during the select period of time are a measure of an aging characteristic of the integrated circuit die.

公开(公告)号：US11368158B2

公开(公告)日：2022-06-21

申请号：US16019297

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer

IPC: H03K19/17764 ,  H03K19/17724 ,  H03K19/17736 ,  G06F30/30 ,  G06F30/39 ,  G06F117/06

Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

公开(公告)号：US20220011811A1

公开(公告)日：2022-01-13

申请号：US17484399

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Anshuman Thakur ,  Atul Maheshwari ,  Mahesh Kumashikar ,  MD Altaf Hossain ,  Ankireddy Nalamalpu

IPC: G06F1/12 ,  G06F9/30

Abstract: A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Systems and methods for transitioning data between the programmable fabric and the processor associated with different clock domains is described.

公开(公告)号：US11216397B2

公开(公告)日：2022-01-04

申请号：US16726132

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Lai Guan Tang ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Chee Hak Teh ,  Md Altaf Hossain

IPC: G06F13/20 ,  G06F13/40

Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.