公开(公告)号：US11157329B2

公开(公告)日：2021-10-26

申请号：US16523009

申请日：2019-07-26

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Hisham Abu-Salah ,  Nir Rosenzweig ,  Efraim Rotem

IPC: G06F1/08 ,  G06F1/324 ,  G06F9/50

Abstract: A processor comprises multiple cores and power management control logic to determine (a) a preliminary frequency for each of the cores and (b) a maximum frequency, based on the preliminary frequencies. The power management control logic is also to determines a dynamic tuning frequency, based on the maximum frequency and a reduction factor. In response to the dynamic tuning frequency for a selected core being greater than the preliminary frequency for that core, the power management control logic is to set the core to a frequency that is at least equal to the dynamic tuning frequency. In response to the preliminary frequency for the selected core being greater than the dynamic tuning frequency for that core, the power management control logic is to set the core to a frequency that is at least equal to the preliminary frequency. Other embodiments are described and claimed.

公开(公告)号：US10990395B2

公开(公告)日：2021-04-27

申请号：US16666111

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Eliezer Weissmann ,  Michael Mishaeli

IPC: G06F9/30 ,  G06F9/54 ,  G06F9/50

Abstract: A system for communication using a register management array circuit is disclosed, including a processor, including a processing core, the processing core including a local core register, a register management array circuit coupled to the local core register, and a remote circuit coupled to the register management array circuit, the remote circuit including a remote register. The register management array circuit includes circuitry to cause the data in the local core register to match the data in the remote register. Methods and circuits are also disclosed.

公开(公告)号：US20210096908A1

公开(公告)日：2021-04-01

申请号：US16586706

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Eliezer Weissmann ,  Robert Valentine ,  Russell Cameron Arnold

IPC: G06F9/48 ,  G06F9/38

Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.

公开(公告)号：US20200278914A1

公开(公告)日：2020-09-03

申请号：US16647563

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： HISHAM ABU SALAH ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jacob Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

公开(公告)号：US10545793B2

公开(公告)日：2020-01-28

申请号：US15720296

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunther ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US10372198B2

公开(公告)日：2019-08-06

申请号：US15686222

申请日：2017-08-25

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Hisham Abu Salah ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Gal Leibovich ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/50

Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

公开(公告)号：US20190212801A1

公开(公告)日：2019-07-11

申请号：US16249103

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/324 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3293 ,  G06F1/3296 ,  G11C7/22 ,  G06F1/3203

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US10345889B2

公开(公告)日：2019-07-09

申请号：US15668762

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/07

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US10324519B2

公开(公告)日：2019-06-18

申请号：US15190377

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Yoni Aizik ,  Doron Rajwan ,  Gal Leibovich ,  Nadav Shulman ,  Hisham Abu Salah

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F13/24

Abstract: In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US20190155362A1

公开(公告)日：2019-05-23

申请号：US16252012

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Efraim Rotem ,  Eliezer Weissmann ,  Avinash N. Ananthakrishnan ,  Dorit Shapira

IPC: G06F1/3228 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3237

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.