公开(公告)号：US11880928B2

公开(公告)日：2024-01-23

申请号：US17723772

申请日：2022-04-19

Applicant: INTEL CORPORATION

Inventor： Scott Janus ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Alexey Supikov ,  Gabor Liktor ,  Carsten Benthin ,  Philip Laws ,  Michael Doyle

IPC: G06T15/06 ,  G06T17/00 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T1/60 ,  G06T15/005 ,  G06T17/005 ,  G06T2210/21

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US11783530B2

公开(公告)日：2023-10-10

申请号：US17677109

申请日：2022-02-22

Applicant: INTEL CORPORATION

Inventor： Karol Szerszen ,  Prasoonkumar Surti ,  Gabor Liktor ,  Karthik Vaidyanathan ,  Sven Woop

IPC: G06T15/00 ,  G06T15/06 ,  G06T15/08 ,  G06T1/20 ,  G06T17/10

CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T15/005 ,  G06T15/08 ,  G06T17/10

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US11688122B2

公开(公告)日：2023-06-27

申请号：US17591166

申请日：2022-02-02

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00 ,  G06F9/48 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

CPC classification number: G06T15/005 ,  G06F9/4881 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US20230143192A1

公开(公告)日：2023-05-11

申请号：US17952628

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Karthik Vaidyanathan

IPC: G06T3/40 ,  G06T5/20

CPC classification number: G06T3/4053 ,  G06T3/4046 ,  G06T5/20 ,  G06T2207/20016 ,  G06T2207/20024

Abstract: Input filtering and sampler acceleration for supersampling is described. An example of a graphics processor comprises a set of processing resources configured to perform a supersampling operation via a convolutional neural network, the set of processing resources including circuitry configured to receive input data for supersampling processing, the input data including data sampled according to a jitter pattern that varies locations for data samples; apply an image filter to the received input data, wherein the image filter includes weighting for pixels that is based at least in part on the jitter pattern; process the input data to generate upsampled data; and apply supersampling processing to the upsampled data.

公开(公告)号：US11461959B2

公开(公告)日：2022-10-04

申请号：US16865587

申请日：2020-05-04

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer Kp ,  Jonathan Kennedy ,  Abhishek R. Appu ,  Jeffery S. Boles ,  Balaji Vembu ,  Michael Apodaca ,  Slawomir Grajewski ,  Gabor Liktor ,  David M. Cimini ,  Andrew T. Lauritzen ,  Travis T. Schluessler ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Kai Xiao ,  Ankur N. Shah ,  Altug Koker

IPC: G06T15/40 ,  G06T1/20 ,  G06T15/30 ,  G06T15/00 ,  G06T11/40 ,  G06T17/20

Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.

公开(公告)号：US11436785B2

公开(公告)日：2022-09-06

申请号：US17223395

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Ingo Wald ,  Gabor Liktor ,  Carsten Benthin ,  Carson Brownlee ,  Johannes Guenther ,  Jefferson D. Amstutz

IPC: G06T15/06 ,  G06T15/00 ,  G06T9/00 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.

公开(公告)号：US20220206990A1

公开(公告)日：2022-06-30

申请号：US17561427

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC: G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US11257180B2

公开(公告)日：2022-02-22

申请号：US16929790

申请日：2020-07-15

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jacek Kwiatkowski ,  Ingo Wald ,  Jefferson Amstutz ,  Johannes Guenther ,  Gabor Liktor ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T1/20 ,  G09G5/36 ,  G06F3/147 ,  G06F9/50 ,  G06F3/14

Abstract: Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment.

公开(公告)号：US11182296B2

公开(公告)日：2021-11-23

申请号：US16566188

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0875 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0855 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

公开(公告)号：US10930051B2

公开(公告)日：2021-02-23

申请号：US16235744

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Scott Janus ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Gabor Liktor ,  Carsten Benthin ,  Philip Laws

IPC: G06T15/06 ,  G06T17/00

Abstract: Apparatus and method for general ray tracing queries. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes associated with a graphics scene; traversal/intersection hardware logic to traverse one or more rays through the acceleration data structure to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; shape processing hardware logic to specify three dimensional (3D) shape data indicating one or more 3D shapes to be used to perform queries with respect to the hierarchical acceleration data structure; query processing hardware logic to execute queries comprising comparisons between nodes of the hierarchical acceleration data structure and the 3D shape data to generate a result indicating overlap between the 3D shapes and the nodes.