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公开(公告)号:US20240004833A1
公开(公告)日:2024-01-04
申请号:US18349386
申请日:2023-07-10
Applicant: Intel Corporation
Inventor: Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
CPC classification number: G06F16/13 , G06F9/3836 , G06F9/30 , G06F9/38 , G06F16/113 , G06F16/172 , G06F9/461 , G06F2201/84 , G06F12/1036
Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
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公开(公告)号:US11704856B2
公开(公告)日:2023-07-18
申请号:US17529938
申请日:2021-11-18
Applicant: Intel Corporation
Inventor: Hugues Labbe , Tomer Bar-On , Gabor Liktor , Andrew T. Lauritzen , John G. Gierach
CPC classification number: G06T15/005 , G06T15/30 , G06T15/40
Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.
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公开(公告)号:US11354848B1
公开(公告)日:2022-06-07
申请号:US16662636
申请日:2019-10-24
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer Kp , Jonathan Kennedy , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Tomer Bar-On , Carsten Benthin , Adam T. Lake , Vasanth Ranganathan , Abhishek R. Appu
IPC: G06T15/08 , G06K9/00 , H04N5/369 , G06T15/60 , G06T15/10 , H04N13/239 , H04N13/344 , H04N5/232 , G02B27/01 , G06T15/00
Abstract: Systems, apparatuses and methods may provide for technology that assigns a first shading rate to a first region of a frame. The technology further assigns a second shading rate to a second region of the frame. The first shading rate indicates that the first region will be rendered at a first resolution, and the second shading rate indicates that the second region will be rendered at a second resolution less than the first resolution. The first and second shading rates are associated with a selection based on a motion vector that corresponds to motion of an object. The object is rendered as part of a scene that includes the first region rendered at the first resolution and the second region rendered at the second resolution.
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公开(公告)号:US11284118B2
公开(公告)日:2022-03-22
申请号:US17111677
申请日:2020-12-04
Applicant: Intel Corporation
Inventor: Jill Boyce , Scott Janus , Itay Kaufman , Archie Sharma , Stanley Baran , Michael Apodaca , Prasoonkumar Surti , Srikanth Potluri , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , Maria Bortman , Tzach Ashkenazi , Jonathan Distler , Atul Divekar , Mayuresh M. Varerkar , Narayan Biswal , Nilesh V. Shah , Atsuo Kuwahara , Kai Xiao , Jason Tanner , Jeffrey Tripp
Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.
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公开(公告)号:US20220005259A1
公开(公告)日:2022-01-06
申请号:US17481656
申请日:2021-09-22
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer KP , Jonathan Kennedy , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Tomer Bar-On , Carsten Benthin , Adam T. Lake , Vasanth Ranganathan , Abhishek R. Appu
IPC: G06T15/08 , G06K9/00 , G02B27/01 , G06T15/60 , H04N5/232 , H04N13/344 , G06T15/10 , H04N5/369 , G06T15/00 , H04N13/239
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
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公开(公告)号:US20210258616A1
公开(公告)日:2021-08-19
申请号:US17111677
申请日:2020-12-04
Applicant: Intel Corporation
Inventor: Jill Boyce , Scott Janus , Itay Kaufman , Archie Sharma , Stanley Baran , Michael Apodaca , Prasoonkumar Surti , Srikanth Potluri , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , Maria Bortman , Tzach Ashkenazi , Jonathan Distler , Atul Divekar , Mayuresh M. Varerkar , Narayan Biswal , Nilesh V. Shah , Atsuo Kuwahara , Kai Xiao , Jason Tanner , Jeffrey Tripp
Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.
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公开(公告)号:US11049266B2
公开(公告)日:2021-06-29
申请号:US16050468
申请日:2018-07-31
Applicant: Intel Corporation
Inventor: Scott Janus , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , James Holland , Narayan Biswal , Yi-Jen Chiu , Qian Xu , Mayuresh Varerkar , Sang-Hee Lee , Stanley Baran , Srikanth Potluri , Jason Ross , Maruthi Sandeep Maddipatla
Abstract: An apparatus comprises a processor to divide a first point cloud data set frame representing a three dimensional space at a first point in time into a matrix of blocks, determine at least one three dimensional (3D) motion vector for at least a subset of blocks in the matrix of blocks, generate a predicted second point cloud data set frame representing a prediction of the three dimensional space at a second point in time by applying the at least one 3D motion vector to the subset of blocks in the matrix of blocks, compare the predicted second point cloud data set frame to a second point cloud data set frame representing a prediction of the three dimensional space at a second point in time to generate a prediction error parameter, and encode the second point cloud data set frame as a function of the first point cloud data set frame and the at least one three dimensional (3D) motion vector when the prediction error factor is beneath an error threshold to produce an encoded second point cloud data set frame.
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公开(公告)号:US20210150798A1
公开(公告)日:2021-05-20
申请号:US17127740
申请日:2020-12-18
Applicant: Intel Corporation
Inventor: Hugues Labbe , Tomer Bar-On , Gabor Liktor , Andrew T. Lauritzen , John G. Gierach
Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.
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公开(公告)号:US10957050B2
公开(公告)日:2021-03-23
申请号:US16688403
申请日:2019-11-19
Applicant: Intel Corporation
Inventor: Hugues Labbe , Tomer Bar-On , John G. Gierach , Gabor Liktor , Andrew T. Lauritzen
IPC: G06T7/194 , G06T15/20 , G06T7/00 , G06T7/11 , H04N19/597 , H04N21/2343 , H04N19/46 , H04N19/587 , H04N21/81 , H04N19/132 , H04N21/478 , H04N19/167 , H04N19/436 , H04N21/4402 , G06T15/50 , H04N21/00 , H04N19/40
Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.
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公开(公告)号:US10706591B2
公开(公告)日:2020-07-07
申请号:US16142866
申请日:2018-09-26
Applicant: Intel Corporation
Inventor: Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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