公开(公告)号：US20190004958A1

公开(公告)日：2019-01-03

申请号：US15640060

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US10145694B2

公开(公告)日：2018-12-04

申请号：US14368350

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Ren Wang ,  Zhonghong Ou ,  Arvind Kumar ,  Kristoffer Fleming ,  Tsung-Yuan C. Tai ,  Timothy J. Gresham ,  John C. Weast ,  Corey Kukis

IPC: G01C21/34 ,  H04B17/318 ,  H04W24/08 ,  H04W4/02

Abstract: Technologies for providing information to a user while traveling include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data. Other embodiments are described and claimed.

公开(公告)号：US20180285105A1

公开(公告)日：2018-10-04

申请号：US15476302

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ren Wang ,  Chunhui Zhang ,  Qixiong J. Bian ,  Bret L. Toll ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/084 ,  G06F12/0842 ,  G06F13/28

CPC classification number: G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3016 ,  G06F9/3834 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/128 ,  G06F13/28 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/62 ,  Y02D10/14

Abstract: Method and apparatus for efficient range-based memory writeback is described herein. One embodiment of an apparatus includes a system memory, a plurality of hardware processor cores each of which includes a first cache, a decoder circuitry to decode an instruction having fields for a first memory address and a range indicator, and an execution circuitry to execute the decoded instruction. Together, the first memory address and the range indicator define a contiguous region in the system memory that includes one or more cache lines. An execution of the decoded instruction causes any instances of the one or more cache lines in the first cache to be invalidated. Additionally, any invalidated instances of the one or more cache lines that are dirty are to be stored to system memory.

公开(公告)号：US09866498B2

公开(公告)日：2018-01-09

申请号：US14580792

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Ren Wang ,  Sameh Gobriel ,  Christian Maciocco ,  Tsung-Yuan C. Tai ,  Ben-Zion Friedman ,  Hang T. Nguyen ,  Namakkal N. Venkatesan ,  Michael A. O'Hanlon ,  Shrikant M. Shah ,  Sanjeev Jain

IPC: H04L12/757 ,  H04L29/08 ,  H04L12/931 ,  H04L12/741

CPC classification number: H04L67/2852 ,  H04L41/0893 ,  H04L45/38 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/00

Abstract: Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.

公开(公告)号：US09847935B2

公开(公告)日：2017-12-19

申请号：US14264912

申请日：2014-04-29

Applicant: Intel Corporation

Inventor： Sameh Gobriel ,  Ren Wang ,  Christian Maciocco ,  Tsung-Yuan Tai

IPC: H04L12/721 ,  H04L12/755 ,  H04L12/743 ,  H04L12/751 ,  H04L12/725

CPC classification number: H04L45/44 ,  H04L45/02 ,  H04L45/021 ,  H04L45/306 ,  H04L45/7453

Abstract: Technologies for distributed table lookup via a distributed router includes an ingress computing node, an intermediate computing node, and an egress computing node. Each computing node of the distributed router includes a forwarding table to store a different set of network routing entries obtained from a routing table of the distributed router. The ingress computing node generates a hash key based on the destination address included in a received network packet. The hash key identifies the intermediate computing node of the distributed router that stores the forwarding table that includes a network routing entry corresponding to the destination address. The ingress computing node forwards the received network packet to the intermediate computing node for routing. The intermediate computing node receives the forwarded network packet, determines a destination address of the network packet, and determines the egress computing node for transmission of the network packet from the distributed router.

公开(公告)号：US20170091090A1

公开(公告)日：2017-03-30

申请号：US14866923

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Ren Wang ,  Andrew J. Herdrich ,  Christopher B. Wilkerson

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/62

Abstract: Apparatus and methods implementing a hardware predictor for reducing performance inversions caused by intra-core data transfer during inter-core data transfer optimization for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache or mid-level cache (MLC) for each core and a shared L3 or last-level cache (LLC). A hardware predictor to monitor accesses to sample cache lines and, based on these accesses, adaptively control the enablement of cache line demotion instructions for proactively demoting cache lines from lower cache levels to higher cache levels, including demoting cache lines from L1 or L2 caches (MLC) to L3 cache (LLC).

公开(公告)号：US09565131B2

公开(公告)日：2017-02-07

申请号：US14580792

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Ren Wang ,  Sameh Gobriel ,  Christian Maciocco ,  Tsung-Yuan C. Tai ,  Ben-Zion Friedman ,  Hang T. Nguyen ,  Namakkal N. Venkatesan ,  Michael A. O'Hanlon ,  Shrikant M. Shah ,  Sanjeev Jain

IPC: H04L12/757 ,  H04L29/08 ,  H04L12/931 ,  H04L12/741

Abstract: Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.

公开(公告)号：US20160227442A1

公开(公告)日：2016-08-04

申请号：US15021827

申请日：2013-11-01

Applicant: INTEL CORPORATION

Inventor： Shun Hao ,  Ren Wang ,  Jr-Shian Tsai ,  Alexander Min ,  Roi Sadan ,  Jianghong Du ,  Arvind Kumar ,  Liraz Zur ,  Longcheng Zhu

IPC: H04W28/22 ,  H04W4/02

CPC classification number: H04W28/22 ,  H04L1/0002 ,  H04L1/0015 ,  H04W4/027

Abstract: Techniques for modifying a transmission rate of a device having a plurality of transmission rate options are described herein. The techniques include a method comprising receiving data from a sensor indicating movement of an electronic device, the electronic device having a plurality of transmission rate options. Fail ratio metrics are gathered. The fail ratio metrics indicate a ratio of failed transmissions to successful transmissions for rate option during device movement. The method includes determining whether a given rate option has a fail ratio above a predetermined threshold; and, if so, disabling the given rate option while the device is moving.

Abstract translation: 这里描述了用于修改具有多个传输速率选项的设备的传输速率的技术。 这些技术包括一种方法，包括从传感器接收指示电子设备的移动的数据，该电子设备具有多个传输速率选项。 收集失败比率指标。 故障比率度量指示在设备移动期间，故障传输与速率选项的成功传输的比率。 该方法包括确定给定速率选项是否具有高于预定阈值的失败比率; 如果是，则在设备移动时禁用给定的速率选项。

公开(公告)号：US20160188474A1

公开(公告)日：2016-06-30

申请号：US14583389

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Ren Wang ,  Andrew J. Herdrich ,  Yen-cheng Liu ,  Herbert H. Hum ,  Jong Soo Park ,  Christopher J. Hughes ,  Namakkal N. Venkatesan ,  Adrian C. Moga ,  Aamer Jaleel ,  Zeshan A. Chishti ,  Mesut A. Ergin ,  Jr-shian Tsai ,  Alexander W. Min ,  Tsung-yuan C. Tai ,  Christian Maciocco ,  Rajesh Sankaran

IPC: G06F12/08

CPC classification number: G06F12/0842 ,  G06F9/45558 ,  G06F12/0813 ,  G06F12/0833 ,  G06F12/0893 ,  G06F12/109 ,  G06F2009/45595 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

Abstract translation: 实现硬件/软件协同优化的方法和设备，以提高NFV和其他生产者 - 消费者工作负载之间的VM间通信的性能和能量。 该装置包括具有多级缓存层级的多核处理器，包括每个核心的L1和L2高速缓存以及共享的最后一级缓存（LLC）。 提供了一个或多个机器级指令，用于主动地将高速缓存行从低级缓存级别降级到更高的高速缓存级别，包括将高速缓存行从L1 / L2高速缓存降级到LLC。 还提供了用于在多插槽NUMA架构系统中实现硬件/软件协同优化的技术，其中高速缓存线可以被选择性地降级并被推送到远程插座中的LLC。 此外，技术是在多插槽系统中实现早期窥探的技术，以减少在远程插槽上访问高速缓存线时的延迟。

公开(公告)号：US12293231B2

公开(公告)日：2025-05-06

申请号：US17471889

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Chenmin Sun ,  Yipeng Wang ,  Rahul R. Shah ,  Ren Wang ,  Sameh Gobriel ,  Hongjun Ni ,  Mrittika Ganguli ,  Edwin Verplanke

IPC: G06F9/50 ,  H04L47/11 ,  H04L47/12 ,  H04L47/125 ,  H04L12/70

Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.