公开(公告)号：US20230422496A1

公开(公告)日：2023-12-28

申请号：US18314862

申请日：2023-05-10

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Tahir Ghani ,  Anand S. Murthy ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Rishabh Mehandru

IPC: H10B41/27 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/528 ,  H01L23/522 ,  H10B41/35 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L23/5283 ,  H01L23/5226 ,  H10B41/35 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: IC devices with logic circuits using vertical transistors with backside source or drain (S/D) regions, and related assemblies and methods, are disclosed herein. An example vertical transistor includes an elongated structure (e.g., a nanoribbon) of one or more semiconductor materials extending between a first side (e.g., a back side) and an opposing second side (e.g., a front side) of a substrate. The first S/D region of the transistor may be provided at the first side of the substrate, while the second S/D region of the transistor may be provided at the second side, with the channel region of the transistor being the portion of the elongated structure between the first and second S/D regions. Implementing various logic circuits using vertical transistors with backside S/D regions may provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.

公开(公告)号：US20230420432A1

公开(公告)日：2023-12-28

申请号：US17846173

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  G02B6/42

CPC classification number: H01L25/167 ,  H01L24/08 ,  H01L23/3107 ,  H01L24/80 ,  H01L24/94 ,  G02B6/4298 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

公开(公告)号：US20230420411A1

公开(公告)日：2023-12-28

申请号：US17846153

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L25/18 ,  H01L24/06 ,  H01L25/50 ,  H01L2224/80379 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L24/05 ,  H01L2224/05647 ,  H01L2224/05567 ,  H01L2224/06102 ,  H01L2224/06183 ,  H01L2224/08146 ,  H01L2224/08137 ,  H01L2224/0557 ,  H01L24/80 ,  H01L24/13 ,  H01L2224/13025 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/80006

Abstract: Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.

公开(公告)号：US20230418508A1

公开(公告)日：2023-12-28

申请号：US17850090

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Pushkar Ranade ,  Sagar Suthram ,  Wilfred Gomes ,  Rajabali Koduri

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/067

Abstract: In one embodiment, an apparatus comprises: a plurality of banks to store data; and a plurality of interconnects, each of the plurality of interconnects to couple a pair of the plurality of banks. In response to a data movement command, a first bank of the plurality of banks is to send data directly to a second bank of the plurality of banks via a first interconnect of the plurality of interconnects. Other embodiments are described and claimed.

公开(公告)号：US20230317557A1

公开(公告)日：2023-10-05

申请号：US17711837

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Wilfred Gomes ,  Pushkar Ranade ,  Sagar Suthram ,  Rajabali Koduri ,  Anand Murthy ,  Tahir Ghani

IPC: H01L23/473 ,  H01L23/36 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L23/473 ,  H01L29/42392 ,  H01L29/0673 ,  H01L23/36

Abstract: Integrated circuit dies, systems, and techniques, are described herein related to single conductivity type transistor circuits operable at low temperatures. A system includes a functional circuit block of an integrated circuit die having a number of non-planar transistors all of the same conductivity type. The system further includes cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.

公开(公告)号：US20230276615A1

公开(公告)日：2023-08-31

申请号：US17680364

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Anand S. Murthy ,  Wilfred Gomes ,  Tahir Ghani ,  Sagar Suthram

IPC: H01L27/108

CPC classification number: H01L27/10841 ,  H01L27/10864

Abstract: Memory devices including vertical transistors and methods of forming such memory devices are disclosed. An example memory device includes a substrate, a BL in the substrate, a channel region over a portion of the BL, a second region over the channel region, an insulator wrapped around at least a portion of the channel region, and a WL. The BL also operates as one of a source region and a drain region of the transistor. The second region is the other one of the source region and the drain region. The WL wraps around at least a portion of the insulator and is separated from the channel region by the insulator. In some embodiments, the BL is formed in a trench in the substrate. An aspect ratio of the BL is in a range from 0.5 to 10. The BL may have a higher conductivity than the channel region.