公开(公告)号：US11086733B2

公开(公告)日：2021-08-10

申请号：US16719896

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Michael Dieter Richter ,  Thomas Hein ,  Wolfgang Anton Spirkl ,  Martin Brox ,  Peter Mayer

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/07

Abstract: Methods, systems, and devices for reporting control information errors are described. A state of a memory array may be monitored during operation. After detecting an error (e.g., in received control information), the memory device may enter a first state (e.g., a locked state) and may indicate to a host device that an error was detected, the state of the memory array before the error was detected , and/or at least a portion of a control signal carrying the received control information. The host device may diagnose a cause of the error based on receiving the indication of the error and/or the copy of the control signal. After identifying and/or resolving the cause of the error, the host device may transmit one or more commands (e.g., unlocking the memory device and returning the memory array to the original state) based on receiving the original state from the memory device.

公开(公告)号：US11036410B2

公开(公告)日：2021-06-15

申请号：US15952569

申请日：2018-04-13

Applicant: Micron Technology, Inc.

Inventor： Peter Mayer ,  Martin Brox ,  Wolfgang Anton Spirkl ,  Marcos Alvarez Gonzalez ,  Casto Salobrena Garcia ,  Andreas Schneider

IPC: G06F12/00 ,  G06F3/06 ,  G06F1/04

Abstract: A method includes varying a number of clock characteristics of each a plurality of memory devices of a memory concurrently, determining a fitness of the memory for each variation of the number of clock characteristics, selecting a particular variation of the number of clock characteristics based on the determined fitness of the memory for the particular variation, changing a setting in each of the plurality of memory devices corresponding to the particular variation to generate an additional variation of the number of clock characteristics, and determining a fitness of the memory for the additional variation.

公开(公告)号：US10998011B2

公开(公告)日：2021-05-04

申请号：US16538376

申请日：2019-08-12

Applicant: Micron Technology, Inc.

Inventor： Peter Mayer ,  Wolfgang Anton Spirkl ,  Michael Dieter Richter ,  Martin Brox ,  Thomas Hein

IPC: G11C11/56 ,  G11C5/14 ,  G11C7/10

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

公开(公告)号：US20210083720A1

公开(公告)日：2021-03-18

申请号：US17078812

申请日：2020-10-23

Applicant: Micron Technology, Inc.

Inventor： Wolfgang Anton Spirkl ,  Michael Dieter Richter ,  Martin Brox ,  Peter Mayer ,  Thomas Hein

IPC: H04B3/487 ,  H04B1/04 ,  H04L25/49 ,  H04B3/32

Abstract: Methods, systems, and devices for pre-distortion of multi-level signaling are described. A device may identify two multi-level signals that are to be transmitted over two transmission lines at the same time. The device may estimate the crosstalk expected to be caused by one of the multi-level signals on the other during propagation. Based on the expected crosstalk, the device may generate a signal that compensates for the expected crosstalk. In some examples, the signal may be a combination of the first signal and a cancelation signal. In some examples, once the compensated signal has been generated, it is transmitted over its respective transmission line at the same time that the other multi-level is transmitted over its respective transmission line.

公开(公告)号：US20210075428A1

公开(公告)日：2021-03-11

申请号：US17099114

申请日：2020-11-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuhiro Takai ,  Maksim Kuzmenka ,  Mani Balakrishnan ,  Martin Brox

IPC: H03L7/087 ,  H03K5/135 ,  H03L7/099 ,  G11C7/22 ,  H03K5/14

Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal, To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

公开(公告)号：US10931287B1

公开(公告)日：2021-02-23

申请号：US16548778

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Yasuhiro Takai ,  Martin Brox ,  Mani Balakrishnan ,  Maksim Kuzmenka

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/18 ,  H03L7/07 ,  H03L7/113

Abstract: Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.

公开(公告)号：US20200293230A1

公开(公告)日：2020-09-17

申请号：US16809449

申请日：2020-03-04

Applicant: Micron Technology, Inc.

Inventor： Wolfgang Anton Spirkl ,  Peter Mayer ,  Martin Brox ,  Michael Dieter Richter ,  Thomas Hein

IPC: G06F3/06 ,  G11C11/22

Abstract: Methods, systems, and devices for receive-side crosstalk cancelation are described. A device that receives multiple signals over different transmission lines may include a circuit for canceling crosstalk. The circuit may include one or more capacitors or inductors that are coupled with the inputs of multiple receive circuits. The circuit may also include a set of resistors that are coupled with the receive circuits. In some cases, the device may dynamically configure the cancelation circuit to provide a particular bandwidth or strength of cancelation. In such cases, the device may configure the circuit autonomously or based on control information from another device.

公开(公告)号：US20200185049A1

公开(公告)日：2020-06-11

申请号：US16681587

申请日：2019-11-12

Applicant: Micron Technology, Inc.

Inventor： Wolfgang Anton Spirkl ,  Michael Dieter Richter ,  Thomas Hein ,  Peter Mayer ,  Martin Brox

IPC: G11C29/10 ,  H04L1/00

Abstract: Methods, systems, and devices for testing of multi-level signaling associated with a memory device are described. A tester may be used to test one or more operations of a memory device. The memory device may be configured to communicate data using a modulation scheme that includes three or more symbols. The tester may be configured to communicate data using a modulation scheme that includes three or fewer symbols. Techniques for testing the memory device using such a tester are described.

公开(公告)号：US20190066738A1

公开(公告)日：2019-02-28

申请号：US15684577

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Martin Brox

IPC: G11C7/10 ,  H01L25/065 ,  H01L25/00

CPC classification number: G11C7/1006 ,  G11C5/04 ,  G11C5/06 ,  G11C5/066 ,  G11C7/1045 ,  G11C2207/105 ,  H01L23/5252 ,  H01L23/5256 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/1434 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A memory device to be placed on a substrate package is configured to operate in multiple modes and support multiple memory densities is provided. The memory device includes a first plurality of electrical contacts corresponding to a first command/address channel, a second plurality of electrical contacts corresponding to a second command/address channel, a third plurality of electrical contacts corresponding to a first data bus, a fourth plurality of electrical contacts corresponding to a second data bus, a memory array including first and second plurality of memory cells, and mode selection circuitry configured to place the memory device in the first mode or the second mode. In the first mode, the first plurality of memory cells is operatively coupled to the first and third pluralities of electrical contacts and the second plurality of memory cells is operatively coupled to the second and fourth plurality of electrical contacts. In the second mode, the first and second pluralities of memory cells are both operatively coupled to the first and third pluralities of electrical contacts.

公开(公告)号：US20240385645A1

公开(公告)日：2024-11-21

申请号：US18659991

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Martin Brox

IPC: G06F1/12

Abstract: Methods, systems, and devices for latency synchronization are described. A memory device may receive a data clock signal having a first rate and may generate a second clock signal having a second rate based on the data clock signal. A sampler may sample a first command signal indicating a command, where the second clock signal includes a first delay. A synchronizer may receive a second command signal from the sampler and a third clock signal from the sampler, where the second command signal and the third clock signal include a second delay. The synchronizer may synchronize a first timing of the second clock signal with a second timing of the third clock signal based on receiving the second command signal and the third clock signal and may output a signal including the second command signal and a synchronized clock signal having the second rate based on the synchronization.