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公开(公告)号：US20250069631A1
公开(公告)日：2025-02-27
申请号：US18771448
申请日：2024-07-12
Applicant: Micron Technology, Inc.
Inventor： Martin Bach , Miljana Nenadovic , Hemant Madhewar , Mani Balakrishnan , Thomas Hein , Martin Brox
Abstract: Methods, systems, and devices for data alignment for memory are described. A memory device may implement individual time adjustments to align portions of a multilevel signal modulated by a modulation scheme with three levels. In some cases, signal paths for generating and transmitting the portions of the multilevel signal may reference a clock signal, and adjustable delay circuits may apply individual delays to the clock signal received at each signal path. For example, a first adjustable delay circuit may apply a first time adjustment to the clock signal received at a first signal path for generating a first portion. And, a second adjustable delay circuit may apply a second time adjustment to the clock signal received at a second signal path for generating a second portion. Applying the time adjustments to the signal paths may align the portions of the multilevel signal in time, compared to the clock signal.
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公开(公告)号：US20210075428A1
公开(公告)日：2021-03-11
申请号：US17099114
申请日：2020-11-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yasuhiro Takai , Maksim Kuzmenka , Mani Balakrishnan , Martin Brox
Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal, To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.
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公开(公告)号：US10931287B1
公开(公告)日：2021-02-23
申请号：US16548778
申请日：2019-08-22
Applicant: Micron Technology, Inc.
Inventor： Yasuhiro Takai , Martin Brox , Mani Balakrishnan , Maksim Kuzmenka
Abstract: Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.
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Patent Agency Ranking
公开(公告)号：US20220085800A1
公开(公告)日：2022-03-17
申请号：US17395069
申请日：2021-08-05
Applicant: Micron Technology, Inc.
Inventor： Martin Brox , Thomas Hein , Mani Balakrishnan
Abstract: Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.
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公开(公告)号：US20200313678A1
公开(公告)日：2020-10-01
申请号：US16368706
申请日：2019-03-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yasuhiro Takai , Maksim Kuzmenka , Mani Balakrishnan , Martin Brox
Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.
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公开(公告)号：US11699993B2
公开(公告)日：2023-07-11
申请号：US17395069
申请日：2021-08-05
Applicant: Micron Technology, Inc.
Inventor： Martin Brox , Thomas Hein , Mani Balakrishnan
Abstract: Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.
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公开(公告)号：US11251796B2
公开(公告)日：2022-02-15
申请号：US17099114
申请日：2020-11-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yasuhiro Takai , Maksim Kuzmenka , Mani Balakrishnan , Martin Brox
Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.
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公开(公告)号：US20210058090A1
公开(公告)日：2021-02-25
申请号：US16548778
申请日：2019-08-22
Applicant: Micron Technology, Inc.
Inventor： Yasuhiro Takai , Martin Brox , Mani Balakrishnan , Maksim Kuzmenka
Abstract: Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.
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