公开(公告)号：US20240128254A1

公开(公告)日：2024-04-18

申请号：US18394185

申请日：2023-12-22

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Seng Kim Ye

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15174 ,  H01L2924/15182 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.

公开(公告)号：US20240074048A1

公开(公告)日：2024-02-29

申请号：US17894070

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Ling Pan ,  Hong Wan Ng ,  Kelvin Tan Aik Boo ,  Seng Kim Ye ,  See Hiong Leow

IPC: H05K1/11 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/111 ,  H01L24/16 ,  H01L25/0657 ,  H05K1/181 ,  H05K3/4644 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16237 ,  H01L2225/0652 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/10159 ,  H05K2201/10734

Abstract: A semiconductor device assembly includes a semiconductor die, a substrate carrying the semiconductor die, and a printed circuit board (PCB) coupled to the substrate. The PCB includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the first solder mask layer through the primary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.

公开(公告)号：US20240071880A1

公开(公告)日：2024-02-29

申请号：US17897155

申请日：2022-08-27

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/16 ,  H01L24/16 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.

公开(公告)号：US11894289B2

公开(公告)日：2024-02-06

申请号：US17982397

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L29/76 ,  H01L29/00 ,  H01L23/48 ,  H01L27/08 ,  H01L49/02 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L27/0805 ,  H01L28/40

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

公开(公告)号：US20230369291A1

公开(公告)日：2023-11-16

申请号：US18225369

申请日：2023-07-24

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Chin Hui Chong ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/50 ,  H01L2225/06572 ,  H01L2225/0651 ,  H01L2224/48227 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

公开(公告)号：US20230282588A1

公开(公告)日：2023-09-07

申请号：US18111517

申请日：2023-02-17

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L23/538 ,  H10B80/00 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16 ,  H01L23/498

CPC classification number: H01L23/5382 ,  H10B80/00 ,  H01L21/4853 ,  H01L24/48 ,  H01L24/32 ,  H01L24/73 ,  H01L24/16 ,  H01L25/162 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2924/1438 ,  H01L2924/1433 ,  H01L2224/48147 ,  H01L2224/48229 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265

Abstract: Semiconductor device assemblies having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device assembly includes a substrate, a controller, and an interposer. The substrate has a top surface and a bottom surface. A cavity extends below the top surface. The controller has a first pin-out pattern. The interposer has a top surface with the first pin-out pattern that is directly connected to the controller and a bottom surface that has a second pin-out pattern. The interposer interconnects the first and second pin-out patterns, and the interposer and the second pin-out pattern are configured to be directly attached to a surface of the substrate in the cavity.

公开(公告)号：US20230066375A1

公开(公告)日：2023-03-02

申请号：US17412604

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: Semiconductor devices including thermally conductive structures are disclosed herein. A heat transfer structure may be thermally coupled to a semiconductor device and directly attached to a signaling layer of a substrate. The heat transfer structure may be configured to remove thermal energy from the semiconductor device and transfer at least a portion of the removed thermal energy directly into the signaling layer for dissipation within the substrate, for transfer through the substrate and out of a corresponding apparatus, or a combination thereof.

公开(公告)号：US20220336419A1

公开(公告)日：2022-10-20

申请号：US17233129

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Chin Hui Chong ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

公开(公告)号：US20220336417A1

公开(公告)日：2022-10-20

申请号：US17232333

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Hong Wan Ng ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

Abstract: Semiconductor devices having multiple substrates and die stacks, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device includes a package substrate, and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device can include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device can also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device can further include a controller die mounted on the substrate. The controller die can be configured to communicate with the second die stack via the routing elements of the substrate. The device can include a mold material encapsulating the first die stack, the second die stack, the substrate, and the controller die.

公开(公告)号：US20220208744A1

公开(公告)日：2022-06-30

申请号：US17137085

申请日：2020-12-29

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye

IPC: H01L25/16 ,  H01L49/02 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.