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公开(公告)号：US11437112B2
公开(公告)日：2022-09-06
申请号：US16681587
申请日：2019-11-12
Applicant: Micron Technology, Inc.
Inventor： Wolfgang Anton Spirkl , Michael Dieter Richter , Thomas Hein , Peter Mayer , Martin Brox
Abstract: Methods, systems, and devices for testing of multi-level signaling associated with a memory device are described. A tester may be used to test one or more operations of a memory device. The memory device may be configured to communicate data using a modulation scheme that includes three or more symbols. The tester may be configured to communicate data using a modulation scheme that includes three or fewer symbols. Techniques for testing the memory device using such a tester are described.
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公开(公告)号：US11409354B2
公开(公告)日：2022-08-09
申请号：US16849746
申请日：2020-04-15
Applicant: Micron Technology, Inc.
Inventor： Martin Brox , Thomas Hein
IPC: G06F1/3234 , G11C11/4074
Abstract: Methods, systems, and devices for multi-voltage operation for driving a multi-mode channel are described. A transmitting device and a receiving device may be coupled via a channel, and the channel may support multiple modes such as a terminated mode and an unterminated mode. A driver may be coupled with the channel, and a voltage supply for the driver may be adjusted based on the mode of the channel, such as based on whether the channel is terminated or unterminated. Adjusting the voltage supply may result in similar or otherwise desirable voltage levels on the channel for each mode of the channel.
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公开(公告)号：US11349526B2
公开(公告)日：2022-05-31
申请号：US17078812
申请日：2020-10-23
Applicant: Micron Technology, Inc.
Inventor： Wolfgang Anton Spirkl , Michael Dieter Richter , Martin Brox , Peter Mayer , Thomas Hein
Abstract: Methods, systems, and devices for pre-distortion of multi-level signaling are described. A device may identify two multi-level signals that are to be transmitted over two transmission lines at the same time. The device may estimate the crosstalk expected to be caused by one of the multi-level signals on the other during propagation. Based on the expected crosstalk, the device may generate a signal that compensates for the expected crosstalk. In some examples, the signal may be a combination of the first signal and a cancelation signal. In some examples, once the compensated signal has been generated, it is transmitted over its respective transmission line at the same time that the other multi-level is transmitted over its respective transmission line.
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公开(公告)号：US11327832B2
公开(公告)日：2022-05-10
申请号：US17150480
申请日：2021-01-15
Applicant: Micron Technology, Inc.
Inventor： Stefan Dietrich , Martin Brox , Michael Dieter Richter , Thomas Hein , Ronny Schneider , Natalija Jovanovic
Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output are transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.
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公开(公告)号：US20220100604A1
公开(公告)日：2022-03-31
申请号：US17493985
申请日：2021-10-05
Applicant: Micron Technology, Inc.
Inventor： Peter Mayer , Thomas Hein , Martin Brox , Wolfgang Anton Spirkl , Michael Dieter Richter
Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.
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Patent Agency Ranking
公开(公告)号：US20220085800A1
公开(公告)日：2022-03-17
申请号：US17395069
申请日：2021-08-05
Applicant: Micron Technology, Inc.
Inventor： Martin Brox , Thomas Hein , Mani Balakrishnan
Abstract: Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.
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公开(公告)号：US20220027296A1
公开(公告)日：2022-01-27
申请号：US17393819
申请日：2021-08-04
Applicant: Micron Technology, Inc.
Inventor： Michael Dieter Richter , Thomas Hein , Martin Brox , Peter Mayer , Wolfgang Anton Spirkl
Abstract: Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, control bits) to be communicated with a second device over a data bus. The first device may partition the data bus into a first set of transmission lines (e.g., based on the quantity of data bits) and a second set of transmission lines (e.g., based on the quantity of control bits). The first device may communicate the quantity of data bits over the first set of transmission lines and communicate the quantity of control bits over the second set of transmission lines. In some cases, the first device may repartition the data bus based on different quantities of data bits and control bits to be communicated with the second device at a different time.
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公开(公告)号：US11138064B2
公开(公告)日：2021-10-05
申请号：US16711354
申请日：2019-12-11
Applicant: Micron Technology, Inc.
Inventor： Michael Dieter Richter , Thomas Hein , Wolfgang Anton Spirkl , Martin Brox , Peter Mayer
Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Error thresholds for a memory device are configurable based on parameters such as a type of data or a location of stored data. When retrieving the data, the memory device tracks or counts errors in the data and determines whether the error threshold has been satisfied. The memory device transmits (e.g., to a host device) an indication of whether the error threshold has been satisfied, and the system is configured to perform functions to correct the errors and/or prevent further errors. The memory device is also configured to identify errors in received commands or to identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).
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公开(公告)号：US11086803B2
公开(公告)日：2021-08-10
申请号：US16579515
申请日：2019-09-23
Applicant: Micron Technology, Inc.
Inventor： Michael Dieter Richter , Thomas Hein , Martin Brox , Peter Mayer , Wolfgang Anton Spirkl
Abstract: Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, control bits) to be communicated with a second device over a data bus. The first device may partition the data bus into a first set of transmission lines (e.g., based on the quantity of data bits) and a second set of transmission lines (e.g., based on the quantity of control bits). The first device may communicate the quantity of data bits over the first set of transmission lines and communicate the quantity of control bits over the second set of transmission lines. In some cases, the first device may repartition the data bus based on different quantities of data bits and control bits to be communicated with the second device at a different time.
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公开(公告)号：US20210193252A1
公开(公告)日：2021-06-24
申请号：US17121314
申请日：2020-12-14
Applicant: Micron Technology, Inc.
Inventor： Markus Balb , Thomas Hein , Heinz Hoenigschmid
Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.
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