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公开(公告)号：US20250062222A1
公开(公告)日：2025-02-20
申请号：US18379668
申请日：2023-10-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tai-Cheng Hou , Da-Jun Lin , Fu-Yu Tsai , Bin-Siang Tsai
IPC: H01L23/522 , H01L21/768
Abstract: The present disclosure is related to a semiconductor device and a fabricating method thereof, and the semiconductor device includes a first dielectric layer and a first conductive structure. The first dielectric layer includes a stacked structure including a low-k dielectric layer, an etching stop layer, and a carbon-rich dielectric layer between the low-k dielectric layer and the etching stop layer, wherein a carbon concentration within the carbon-rich dielectric layer is above 15%. The first conductive structure is disposed in the first dielectric layer.
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公开(公告)号：US20250017022A1
公开(公告)日：2025-01-09
申请号：US18888142
申请日：2024-09-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Yi-AN Shih , Bin-Siang Tsai , Fu-Yu Tsai
Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.
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公开(公告)号：US20240243057A1
公开(公告)日：2024-07-18
申请号：US18124591
申请日：2023-03-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Bin-Siang Tsai , Fu-Yu Tsai
IPC: H01L23/522 , H01L21/768 , H01L23/00 , H01L27/08
CPC classification number: H01L23/5223 , H01L21/76805 , H01L23/5226 , H01L24/05 , H01L24/11 , H01L27/0805 , H01L2224/05026 , H01L2224/116 , H01L2924/19041 , H01L2924/30105
Abstract: An integrated circuit includes a substrate, an interconnection layer, an insulation layer, a metal bump structure, and a metal-insulator-metal capacitor. The interconnection layer is disposed above the substrate. The interconnection layer includes an interlayer dielectric layer and an interconnection structure disposed in the interlayer dielectric layer. The insulation layer is disposed on the interconnection layer, the metal bump structure is disposed on the insulation layer, and the metal-insulator-metal capacitor is disposed conformally on the metal bump structure and the insulation layer. A manufacturing method of the integrated circuit includes the following steps.
The interconnection layer is formed above the substrate. The insulation layer is formed on the interconnection layer, the metal bump structure is formed on the insulation layer, and the metal-insulator-metal capacitor is formed conformally on the metal bump structure and the insulation layer.-
公开(公告)号：US20240081154A1
公开(公告)日：2024-03-07
申请号：US18504176
申请日：2023-11-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tai-Cheng Hou , Fu-Yu Tsai , Bin-Siang Tsai , Da-Jun Lin , Chau-Chung Hou , Wei-Xin Gao
Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
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公开(公告)号：US20240032433A1
公开(公告)日：2024-01-25
申请号：US18376820
申请日：2023-10-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Tai-Cheng Hou , Bin-Siang Tsai , Ting-An Chien
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a top electrode on the MTJ, a trapping layer in the top electrode for trapping hydrogen, a first inter-metal dielectric (IMD) layer on the MTJ, and a first metal interconnection in the first IMD layer and on the top electrode. Preferably, a top surface of the trapping layer is lower than a bottom surface of the first IMD layer.
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Patent Agency Ranking
公开(公告)号：US20230413690A1
公开(公告)日：2023-12-21
申请号：US18242550
申请日：2023-09-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Wei Su , Da-Jun Lin , Chih-Wei Chang , Bin-Siang Tsai , Ting-An Chien
CPC classification number: H10N70/063 , H10B63/00 , H10N70/028 , H10N70/041 , H10N70/841 , H10N70/8833
Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.
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公开(公告)号：US20230354715A1
公开(公告)日：2023-11-02
申请号：US18215162
申请日：2023-06-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H10N50/10 , H01L21/768 , H01L21/762 , H10N50/80
CPC classification number: H10N50/10 , H01L21/76802 , H01L21/762 , H10N50/80 , H10N35/01
Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
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公开(公告)号：US11737370B2
公开(公告)日：2023-08-22
申请号：US17141194
申请日：2021-01-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H01L41/47 , H10N50/10 , H01L21/768 , H01L21/762 , H10N50/80 , H10N35/01
CPC classification number: H10N50/10 , H01L21/762 , H01L21/76802 , H10N50/80 , H10N35/01
Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
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公开(公告)号：US20230260937A1
公开(公告)日：2023-08-17
申请号：US18138752
申请日：2023-04-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Bin-Siang Tsai , Fu-Yu Tsai
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/45 , H01L2224/05124 , H01L2224/45147 , H01L2224/45464
Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.
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公开(公告)号：US11723215B2
公开(公告)日：2023-08-08
申请号：US17106214
申请日：2020-11-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Yi-An Shih , Bin-Siang Tsai , Fu-Yu Tsai
Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.
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