公开(公告)号：US20170098710A1

公开(公告)日：2017-04-06

申请号：US15379486

申请日：2016-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

公开(公告)号：US20170062484A1

公开(公告)日：2017-03-02

申请号：US14872156

申请日：2015-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L27/12 ,  H01L29/51 ,  H01L29/24 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L21/441 ,  H01L29/786 ,  H01L23/528

CPC classification number: H01L27/1237 ,  H01L21/02107 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/441 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/512 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.

Abstract translation: 本发明提供一种半导体器件及其形成方法，半导体器件包括衬底，氧化物半导体层，两个源极/漏极区，高k电介质层和底部氧化物层。 氧化物半导体层设置在设置在基板上的第一绝缘层上。 源极/漏极区域设置在氧化物半导体层上。 高k电介质层覆盖氧化物半导体层和源极结构以及漏极区域。 底部氧化物层设置在高k电介质层和源/漏区之间，其中底部氧化物层覆盖源/漏区和氧化物半导体层。

公开(公告)号：US09455351B1

公开(公告)日：2016-09-27

申请号：US14841731

申请日：2015-09-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/66969

Abstract: An oxide semiconductor field effect transistor (OS FET) device includes a first dielectric layer formed on a substrate, an oxide semiconductor (OS) island formed on the first dielectric layer, a first gate electrode formed on the OS island, a gate dielectric layer formed in between the first gate electrode and the OS island, a patterned hard mask layer formed on a top surface of the first gate electrode, an etch stop layer covering a top surface of the patterned hard mask layer and sidewalls of the first gate electrode, and a source electrode and a drain electrode formed on the OS island. At least one of the source electrode and the drain electrode partially overlaps the etching stop layer on the sidewalls of the first gate electrode.

Abstract translation: 一种氧化物半导体场效应晶体管（OS FET）器件包括形成在基板上的第一介电层，形成在第一介电层上的氧化物半导体（OS）岛，形成在OS岛上的第一栅电极，形成的栅介质层 在第一栅电极和OS岛之间，形成在第一栅电极的顶表面上的图案化硬掩模层，覆盖图案化硬掩模层的顶表面和第一栅电极的侧壁的蚀刻停止层，以及 形成在OS岛上的源电极和漏电极。 源极电极和漏极电极中的至少一个部分地与第一栅电极的侧壁上的蚀刻停止层重叠。

公开(公告)号：US20160079067A1

公开(公告)日：2016-03-17

申请号：US14949896

申请日：2015-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC: H01L21/28

CPC classification number: H01L21/28158 ,  H01L21/28114 ,  H01L21/28185 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.

Abstract translation: 提供了包括基板，间隔物和具有U形轮廓的高k电介质层的半导体器件。 位于基板上的间隔件围绕并限定沟槽。 具有U形轮廓的高k电介质层位于沟槽中，并且具有U形轮廓的高k电介质层露出沟槽的侧壁的上部。

公开(公告)号：US20150348971A1

公开(公告)日：2015-12-03

申请号：US14825165

申请日：2015-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Abstract translation: 半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。 半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。 与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。 第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。

公开(公告)号：US20150263170A1

公开(公告)日：2015-09-17

申请号：US14723447

申请日：2015-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Chun-Yuan Wu ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Yu-Shu Lin ,  Szu-Hao Lai

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L21/324 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3003 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636

Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成两个栅极。 在栅极旁边的基板中形成凹部。 在凹部的表面上进行表面改性处理，以改变凹部的形状并改变表面的内容物。

公开(公告)号：US09018087B2

公开(公告)日：2015-04-28

申请号：US14013429

申请日：2013-08-29

Applicant: United Microelectronics Corp.

Inventor： Hung-Lin Shih ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/30621 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 在基板上形成虚拟栅极结构，其中虚拟栅极结构包括虚拟栅极和堆叠的硬掩模，并且堆叠的硬掩模从底部至顶部包括第一硬掩模层和第二硬掩模层。 在虚拟栅极结构的侧壁上形成间隔物。 在基板上形成掩模层。 在掩模层中形成与第二硬掩模层对应的开口。 去除第二个硬掩模层。 去除掩模层。 执行干蚀刻工艺以去除第一硬掩模层，其中干蚀刻工艺使用NF 3和H 2作为蚀刻剂。

公开(公告)号：US20150079777A1

公开(公告)日：2015-03-19

申请号：US14029824

申请日：2013-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/28

CPC classification number: H01L21/28176 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.

Abstract translation: 提供一种制造具有金属栅极的半导体器件的方法。 提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底。 第一导电型晶体管具有第一沟槽，第二导电型晶体管具有第二沟槽。 在第一沟槽中形成第一功函数层。 对第一功函数层进行硬化处理。 对第一功函数层的一部分进行软化处理。 执行拉回步骤以去除第一功函数层的部分。 在第二沟槽中形成第二功函数层。 在第一沟槽和第二沟槽中形成低电阻金属层。

公开(公告)号：US08962486B2

公开(公告)日：2015-02-24

申请号：US14142940

申请日：2013-12-30

Applicant: United Microelectronics Corp.

Inventor： Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Po-Chun Chen

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/76802

Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.

Abstract translation: 本发明提供一种在半导体衬底上形成开口的方法。 首先，提供基板。 然后在基板上形成介电层和盖层。 电介质层的厚度和盖层的厚度之比基本上在15和1.5之间。 接下来，在盖层上形成图案化的氮化硼层。 最后，通过使用图案化的硬掩模作为掩模来执行蚀刻工艺，以蚀刻覆盖层和电介质层，以在盖层和电介质层中形成开口。

公开(公告)号：US20140332824A1

公开(公告)日：2014-11-13

申请号：US14340267

申请日：2014-07-24

Applicant: United Microelectronics Corp.

Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/16 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.

Abstract translation: 描述用于形成FinFET的半导体结构。 半导体结构包括半导体衬底，衬底上的FinFET的多个奇数鳍片，以及FinFET的奇数鳍片之间的衬底上的FinFET的多个偶数鳍片。 FinFET的奇数鳍从衬底定义。 FinFET的均匀鳍片与宽度和材料中的至少一个中的FinFET的奇数鳍不同，并且可以与FinFET的高度的奇数鳍不同。