公开(公告)号：US20110101514A1

公开(公告)日：2011-05-05

申请号：US13005218

申请日：2011-01-12

Applicant: Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

Inventor： Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

IPC: H01L23/34

CPC classification number: H05K3/301 ,  H01L2924/0002 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradeable.

Abstract translation: 一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。 半导体器件的每个接合焊盘都设置在其单个边缘附近。 优选地，半导体器件的至少一部分被暴露。 对准装置附接到载体基板。 可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。 优选地，对准装置将垂直安装的半导体器件封装相对于载体衬底垂直固定。 接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。 垂直安装的半导体器件封装也可以容易地用户升级。

公开(公告)号：US20100155966A1

公开(公告)日：2010-06-24

申请号：US12714130

申请日：2010-02-26

Applicant: Walter L. Moden

Inventor： Walter L. Moden

IPC: H01L23/485

CPC classification number: H01L24/81 ,  H01L21/485 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5382 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19107 ,  H05K1/141 ,  H05K3/305 ,  H05K3/328 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/10477 ,  H05K2201/10727 ,  H05K2203/0415 ,  H05K2203/049 ,  Y02P70/613 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the second surface, and substrate pads on the second surface, adjacent to the opening. Bond pads of the semiconductor die are aligned with the opening through the substrate. Intermediate conductive elements, such as bond wires, extend from bond pads of the semiconductor die, through the opening, to substrate pads on the opposite, second surface of the substrate. An encapsulant, which fills the opening and covers the intermediate conductive elements, protrudes beyond a plane in which the second surface of the substrate is located. Discrete conductive elements, such as solder balls, may protrude from the contact pads of the substrate.

Abstract translation: 半导体器件组件包括与衬底的第一表面相邻的衬底和半导体管芯。 衬底还包括与第一表面相对的第二表面，从第一表面和第二表面延伸的开口，第二表面上的接触焊盘以及与开口相邻的第二表面上的衬底焊盘。 半导体管芯的焊盘与通过衬底的开口对准。 诸如接合线的中间导电元件从半导体管芯的接合焊盘延伸通过开口，延伸到衬底的相对的第二表面上的衬底焊盘。 填充开口并覆盖中间导电元件的密封剂突出超过衬底的第二表面所在的平面。 离散导电元件，例如焊球，可能从基板的接触垫突出。

公开(公告)号：US07408255B2

公开(公告)日：2008-08-05

申请号：US11263509

申请日：2005-10-31

Applicant: David J. Corisis ,  Walter L. Moden ,  Leonard E. Mess ,  Larry D. Kinsman

Inventor： David J. Corisis ,  Walter L. Moden ,  Leonard E. Mess ,  Larry D. Kinsman

IPC: H01L23/02

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.

Abstract translation: 公开了可堆叠形成高密度部件的球栅阵列封装以及堆叠球栅阵列的方法。 球栅阵列封装包括柔性或刚性衬底。 球栅阵列封装还包括用于连接到半导体器件的电路的阻抗的基本匹配的布置。

公开(公告)号：US07279797B2

公开(公告)日：2007-10-09

申请号：US11028361

申请日：2005-01-03

Applicant: David J. Corisis ,  Walter L. Moden ,  Leonard E. Mess ,  Larry D. Kinsman

Inventor： David J. Corisis ,  Walter L. Moden ,  Leonard E. Mess ,  Larry D. Kinsman

IPC: H01L23/43

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.

Abstract translation: 可堆叠形成高密度组件的球栅阵列封装以及堆叠球栅阵列的方法。 球栅阵列封装包括柔性或刚性衬底。 球栅阵列封装还包括用于连接到半导体器件的电路的阻抗的基本匹配的布置。

公开(公告)号：US07105380B2

公开(公告)日：2006-09-12

申请号：US10395477

申请日：2003-03-24

Applicant: Walter L. Moden ,  John O. Jacobson

Inventor： Walter L. Moden ,  John O. Jacobson

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: G01R1/04 ,  G01R1/0483 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2924/01019 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of using adhesive tape to temporarily retain a die being temporarily held in a fixture during testing and burn-in. The method of the present invention uses a die cut piece of adhesively coated tape to hold a die in a test and burn-in fixture. Upon subsequent heating of the tape beyond the normal operating range of the adhesive coating on the tape, the die is removed from the tape, the tape is removed from the test and burn-in fixture, and the remaining adhesive, if any, is removed from the test and burn-in fixture.

公开(公告)号：US06979598B2

公开(公告)日：2005-12-27

申请号：US10799948

申请日：2004-03-12

Applicant: Tongbi Jiang ,  Syed S. Ahmad ,  Walter L. Moden

Inventor： Tongbi Jiang ,  Syed S. Ahmad ,  Walter L. Moden

IPC: H01L21/66 ,  H01L23/495 ,  H01L21/44

CPC classification number: H01L23/49513 ,  H01L23/4951 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract translation: 本发明涉及一种使用在预定图案上施加的湿膜粘合剂将引线框架附接到优质裸片，引线框架的引线指或两者的引线框架的方法。 通过将粘合剂应用于识别好的骰子，可以通过在整个晶片上施加粘合剂的过程节省时间和材料。 通过使用湿膜将引线框架连接到良好的裸片上，如果良好的芯片随后测试不可接受，则可以从良好的模具中去除引线框架以进行返工。

公开(公告)号：US06974725B2

公开(公告)日：2005-12-13

申请号：US10808713

申请日：2004-03-23

Applicant: Walter L. Moden ,  Larry D. Kinsman ,  Warren M. Farnworth

Inventor： Walter L. Moden ,  Larry D. Kinsman ,  Warren M. Farnworth

IPC: H01L23/31 ,  H01L23/485 ,  H01L21/44

CPC classification number: H01L24/10 ,  H01L23/3107 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00013 ,  H01L2924/013

Abstract: A method for forming an electrical contact for a semiconductor device comprises the steps of providing a semiconductor wafer section having a major surface with a plurality of conductive pads thereon and electrically coupling each pad with an elongated electrical interconnect. Next, each electrical interconnect is encased in a dielectric and the dielectric is sectioned to expose a portion of each interconnect. An inventive structure which can be formed by the inventive method is also described.

Abstract translation: 一种用于形成用于半导体器件的电接触的方法包括以下步骤：提供具有主表面的半导体晶片部分，其上具有多个导电焊盘，并使每个焊盘与细长的电互连电连接。 接下来，每个电互连被封装在电介质中，并且电介质被分段以暴露每个互连的一部分。 还描述了可以通过本发明方法形成的本发明的结构。

公开(公告)号：US06825547B2

公开(公告)日：2004-11-30

申请号：US10137766

申请日：2002-05-02

Applicant: Warren M. Farnworth ,  Larry D. Kinsman ,  Walter L. Moden

Inventor： Warren M. Farnworth ,  Larry D. Kinsman ,  Walter L. Moden

IPC: H01L2348

CPC classification number: H01L24/11 ,  H01L23/485 ,  H01L24/02 ,  H01L24/45 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2224/48 ,  H01L2924/00

Abstract: A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the semiconductor wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate and establishing an electrical connection between the bond pad and the terminal. Preferably, an electrically conductive material is disposed between the bond pad and the terminal to establish an electrically conductive bond between the semiconductor device and the carrier substrate.

Abstract translation: 一种垂直安装的半导体器件，包括设置在其边缘上的至少一个接合焊盘。 接合焊盘包括设置在其上的导电凸块。 半导体器件还可以包括保护外涂层。 本发明还包括一种制造半导体器件的方法，包括在半导体晶片中形成断开的切口，将电路迹线重定向到每个凹口中，以及沿着凹口划分半导体晶片，以在所得半导体的边缘上形成接合焊盘 设备。 将半导体器件附接到载体衬底的方法包括使半导体器件定向，使得接合焊盘与载体衬底的相应端子对准并且在接合焊盘和端子之间建立电连接。 优选地，导电材料设置在接合焊盘和端子之间，以在半导体器件和载体衬底之间建立导电接合。

公开(公告)号：US06740545B2

公开(公告)日：2004-05-25

申请号：US10309643

申请日：2002-12-03

Applicant: Jerrold L. King ,  J. Mike Brooks ,  Walter L. Moden

Inventor： Jerrold L. King ,  J. Mike Brooks ,  Walter L. Moden

IPC: H01L2144

CPC classification number: H01L23/3142 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1815 ,  Y10S438/926 ,  Y10S438/928 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound packaging during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract translation: 半导体管芯包括沉积在其上的金属层，用于增强管芯和模具复合封装之间的附着力。 金属层基本上不含氧化物。 通过电镀或无电涂覆技术将模具涂覆有一层或多层铜（Cu）和/或钯（Pd）。 金属层提供均匀的润湿表面，用于在包封期间模具与模具复合包装的更好的附着。 增加的粘附力降低了模具从包装中的分层势。

公开(公告)号：US06738263B2

公开(公告)日：2004-05-18

申请号：US10222243

申请日：2002-08-16

Applicant: David J. Corisis ,  Jerry M. Brooks ,  Walter L. Moden

Inventor： David J. Corisis ,  Jerry M. Brooks ,  Walter L. Moden

IPC: H05K111

CPC classification number: H01L24/06 ,  H01L23/3107 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.

Abstract translation: 可堆叠的FBGA封装被构造成使得导电元件沿着安装到FBGA的集成电路（IC）器件的外周放置。 导电元件也具有足够的尺寸，使得它们延伸超过IC器件的底表面或顶表面，包括布线互连和封装材料，因为导电元件与位于或之下的FBGA接触以形成叠层。 诸如存储器芯片的IC器件安装在形成FBGA的一部分的印刷电路板基板的第一表面上。 引线用于将IC器件连接到印刷电路板基板，并且密封剂用于将IC器件和导线元件的基体内部和外部的电线包含在IC器件中。