公开(公告)号：US09760467B2

公开(公告)日：2017-09-12

申请号：US14659529

申请日：2015-03-16

Applicant: CA, INC.

Inventor： Mark Jacob Addleman

IPC: H04L12/26 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F11/3466 ,  G06F11/3447 ,  G06F11/3452 ,  G06F11/36 ,  G06F2201/865 ,  G06F2201/87

Abstract: An application performance monitoring system monitors a system having multiple components, automatically calculates a performance metric for the system, and determines a relationship between components of the software system that effect the performance metric. The system is configured to automatically generate a model of behavior of the performance metric using a genetic search process that randomly creates a set of functions and evolves those functions over multiple generations with evolution being skewed by a rule based on the determined relationship between components.

公开(公告)号：US09760352B2

公开(公告)日：2017-09-12

申请号：US14799625

申请日：2015-07-15

Applicant: FUJITSU LIMITED

Inventor： Shusaku Nakashima ,  Toshiya Naito

IPC: G06F9/45 ,  G06F11/34

CPC classification number: G06F8/443 ,  G06F8/4452 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865

Abstract: A program optimization method, executed by an arithmetic processing device, includes collecting profile information including a runtime analysis result by causing a computer to execute an original program to be optimized, calculating a calculation wait time based on the profile information, and generating a tuned-up program, when the calculation wait time is longer than a first threshold, by inserting an SIMD operation control line that performs an SIMD operation for an instruction in IF statement in the loop when an SIMD instruction ratio in the loop in the original program is lower than a second threshold.

公开(公告)号：US09760288B2

公开(公告)日：2017-09-12

申请号：US14624990

申请日：2015-02-18

Applicant: International Business Machines Corporation

Inventor： Matthew R. Kilner ,  David K. Siegwart

IPC: G06F3/06 ,  G06F11/34 ,  G06F11/07 ,  G06F12/02

CPC classification number: G06F11/079 ,  G06F3/0608 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/3452 ,  G06F11/3466 ,  G06F11/3476 ,  G06F12/023 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2206/1004 ,  G06F2212/1044

Abstract: A method of determining causes of external fragmentation in a memory. The method includes collecting information associated with release of an area of the memory by an application, storing the information in the area of the memory, and analyzing the information to determine why the area of the memory has not been reallocated to any application. In embodiments wherein a first portion of an area of a memory is allocated to an application by an allocator and a second portion of the area of the memory is released by the allocator, the method includes storing in the second portion of the area of the memory an indicator indicating that the second portion is a remaining portion, colleting information associated with release of the second portion, storing the information in the second portion, and analyzing the information to determine why the second portion is not reallocated to any application.

公开(公告)号：US20170255527A1

公开(公告)日：2017-09-07

申请号：US15583975

申请日：2017-05-01

Applicant: Citrix Systems, Inc.

Inventor： Chris WADE ,  Stanislaw SKOWRONEK

IPC: G06F11/14

CPC classification number: G06F11/1469 ,  G06F11/1438 ,  G06F11/3003 ,  G06F11/3096 ,  G06F11/3476 ,  G06F11/36 ,  G06F2201/815 ,  G06F2201/835 ,  G06F2201/84 ,  G06F2201/865

Abstract: A first computing device is provided for rolling back a computing environment. The computing device includes processors configured to acquire a stream containing entries including snapshot entries, memory entries, and input/output entries wherein each entry includes information and is associated with a timestamp. The processors are further configured to receive a snapshot entry associated with a first timestamp, revert to a memory state using information provided in at least one memory entry associated with a timestamp after the first timestamp, and re-execute a previously executed process, wherein the re-execution of the process is started using the first timestamp, information from the received snapshot entry, and information for input/output operations corresponding to the input/output entries associated with timestamps after the first timestamp.

公开(公告)号：US09747440B2

公开(公告)日：2017-08-29

申请号：US13937462

申请日：2013-07-09

Applicant: QUALCOMM Incorporated

Inventor： Rajarshi Gupta ,  Mark Bapst ,  Mohammad H Reshadi ,  Samir Kumar

IPC: G06F21/55 ,  G06F9/445 ,  G06F21/31 ,  H04L29/06 ,  H04W12/12 ,  G06N5/04 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F21/55 ,  G06F8/61 ,  G06F8/65 ,  G06F11/3013 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3476 ,  G06F21/316 ,  G06F21/552 ,  G06F2201/865 ,  G06N5/043 ,  H04L63/1425 ,  H04W12/12

Abstract: Methods, systems and devices for generating data models in a client-cloud communication system may include applying machine learning techniques to generate a first family of classifier models that describe a cloud corpus of behavior vectors. Such vectors may be analyzed to identify factors in the first family of classifier models that have the highest probability of enabling a mobile device to better determine whether a mobile device behavior is malicious or benign. Based on this analysis, a second family of classifier models may be generated that identify significantly fewer factors and data points as being relevant for enabling the mobile device to better determine whether the mobile device behavior is malicious or benign based on the determined factors. A mobile device classifier module based on the second family of classifier models may be generated and made available for download by mobile devices, including devices contributing behavior vectors.

公开(公告)号：US09703551B2

公开(公告)日：2017-07-11

申请号：US14262864

申请日：2014-04-28

Applicant: Nishant Thorat

Inventor： Nishant Thorat

IPC: G06F9/44 ,  G06F9/445 ,  G06F11/34

CPC classification number: G06F8/71 ,  G06F9/44521 ,  G06F11/3013 ,  G06F11/302 ,  G06F11/3093 ,  G06F11/34 ,  G06F11/3466 ,  G06F2201/865

Abstract: A method includes determining a system library method based on a configuration file in an application library. The method also includes generating a wrapper method for the system library method, wherein the wrapper method includes a first instruction to invoke the system library method, and a second instruction to invoke a method in an external library. The method further includes replacing a third instruction that invokes the system library method with a fourth instruction that invokes the wrapper method. A binary class in a plurality of binary classes in the application library comprises the third instruction.

公开(公告)号：US09691117B2

公开(公告)日：2017-06-27

申请号：US13994720

申请日：2011-11-30

Applicant: Arie Narkis

Inventor： Gil Fridman ,  Arie Narkis

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/80 ,  G09G5/36 ,  G06F9/44 ,  G06F9/445 ,  G06F11/34

CPC classification number: G06T1/20 ,  G06F9/44 ,  G06F9/44521 ,  G06F11/3466 ,  G06F2201/865 ,  G06T15/005 ,  G06T15/80 ,  G09G5/363

Abstract: Data may be streamed out of a graphics pipeline during run time without preprogramming the stream out. A command stream may be captured, draw commands monitored, and shader output definitions may be parsed to determine how to stream out shader data, for example for debugging. Data may be streamed out from an application without using the application's original code.

公开(公告)号：US09690588B2

公开(公告)日：2017-06-27

申请号：US15155204

申请日：2016-05-16

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Michael W. Chynoweth ,  Ofer Levy ,  Jason W. Brandt ,  Angela Schmid

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/34

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/30098 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/865 ,  G06F2201/88

Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.

公开(公告)号：US20170153960A1

公开(公告)日：2017-06-01

申请号：US15363856

申请日：2016-11-29

Applicant: FUJITSU LIMITED

Inventor： Tadanobu Tsunoda ,  Naoki Nishiguchi ,  Akira FUJII ,  Tatsuro Matsumoto

IPC: G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3476 ,  G06F11/3003 ,  G06F11/302 ,  G06F11/3072 ,  G06F11/3438 ,  G06F17/40 ,  G06F2201/865

Abstract: An information processing device includes a memory and a processor coupled to the memory and configured to determine a priority level of an application that provides a service depending on a predetermined state, using relation information between the predetermined states, and control storing log of the application in the memory, depending on the priority level of the application.

公开(公告)号：US09665347B2

公开(公告)日：2017-05-30

申请号：US14582812

申请日：2014-12-24

Applicant: ARM Limited

Inventor： David Raymond Lutz ,  Neil Burgess ,  Christopher Neal Hinds

IPC: G06F5/00 ,  G06F7/483 ,  G06F7/499 ,  G06F9/30 ,  G06F17/16 ,  H03M7/12 ,  H03M7/24 ,  G06F11/34 ,  G06F11/36 ,  G06F5/01 ,  G06F7/38 ,  G06F7/48 ,  G06F7/507 ,  G06F9/38 ,  G06F7/506

CPC classification number: G06F7/483 ,  G06F5/012 ,  G06F7/38 ,  G06F7/48 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/49921 ,  G06F7/49942 ,  G06F7/506 ,  G06F7/507 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3885 ,  G06F11/3404 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/3636 ,  G06F11/3644 ,  G06F11/3648 ,  G06F17/16 ,  G06F2201/865 ,  G06F2207/483 ,  H03M7/12 ,  H03M7/24

Abstract: An apparatus comprises processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a scalar value comprising an alternative representation of said binary value.