公开(公告)号：US20230266915A1

公开(公告)日：2023-08-24

申请号：US18306068

申请日：2023-04-24

Applicant: KIOXIA CORPORATION

Inventor： Yuki SASAKI ,  Shinichi KANNO

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F3/0611 ,  G06F12/0246 ,  G06F2212/7201

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.

公开(公告)号：US11726906B2

公开(公告)日：2023-08-15

申请号：US17130485

申请日：2020-12-22

Applicant: Kioxia Corporation

Inventor： Shinichi Kanno

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/02 ,  G06F2212/1036 ,  G06F2212/222 ,  G06F2212/7201 ,  G06F2212/7209

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.

公开(公告)号：US20230251890A1

公开(公告)日：2023-08-10

申请号：US18161091

申请日：2023-01-30

Applicant: Nutanix, Inc.

Inventor： Binny Sher GILL

IPC: G06F9/455 ,  G06F9/4401 ,  G06F12/02

CPC classification number: G06F9/45558 ,  G06F9/4418 ,  G06F12/0246 ,  G06F2009/45575 ,  G06F2009/45583 ,  G06F2212/7201

Abstract: Upon receiving a request to hibernate a hypervisor of a virtualization system running on a first computer, acts are carried out to capture a state of the hypervisor, where the state of the hypervisor comprises hypervisor logical resource parameters and an execution state of the hypervisor. After hibernating the hypervisor by quiescing the hypervisor and storing the state of the hypervisor into a data structure, the data structure is moved to a different location. At a later moment in time, the data structure is loaded onto a second computing machine and restored. The restore operation restores the hypervisor and all of its state, including all of the virtual machines of the hypervisor as well as all of the virtual disks and other virtual devices of the virtual machines. Differences between the first computing machine and the second computing machine are reconciled before execution of the hypervisor on the second machine.

公开(公告)号：US11720490B2

公开(公告)日：2023-08-08

申请号：US17446519

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Yuehhung Chen ,  Chih-Kuo Kao ,  Fangfang Zhu ,  Jiangli Zhu

IPC: G06F12/02 ,  G06F12/0891 ,  G06F3/06

CPC classification number: G06F12/0292 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0891 ,  G06F2212/7201

Abstract: Responsive to receiving a table flush command, a first portion of an address mapping table is identified. A first flush operation with respect to a first portion of the address mapping table is performed. Responsive to receiving at least one memory access command, flush operations for a subsequent portion of the address mapping table is suspended. At least one memory access operation specified by the at least one memory access command is performed. A second flush operation with respect to the subsequent portion of the address mapping table is performed.

公开(公告)号：US11709781B2

公开(公告)日：2023-07-25

申请号：US17887917

申请日：2022-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeju Kim ,  Youngho Park ,  Sangyoon Oh ,  Hyungchul Jang ,  Jekyeom Jeon

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/7201

Abstract: A method of managing data in a storage device is provided. The storage device includes a plurality of nonvolatile memory chips each including a plurality of pages. A first data object is received from an external host device. The first data object has an unfixed size and corresponds to a first logical address which is a single address. Based on determining that it is impossible to store the first data in a single page among the plurality of pages, a buffering policy for the first data object is set based on at least one selection parameter. While mapping the first logical address of the first data object and a first physical address of pages in which the first data object is stored, a first buffering direction representing the buffering policy for the first data object is stored with a mapping result.

公开(公告)号：US11704235B2

公开(公告)日：2023-07-18

申请号：US17335512

申请日：2021-06-01

Applicant: Kioxia Corporation

Inventor： Shogo Ochiai ,  Nobuaki Tojo

IPC: G06F12/02 ,  G06F12/12 ,  G06F12/08 ,  G06F12/123 ,  G06F12/0891

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F12/0891 ,  G06F12/123 ,  G06F2212/7201

Abstract: A memory system of an embodiment includes a nonvolatile memory, a primary cache memory, a secondary cache memory, and a processor. The processor performs address conversion by using logical-to-physical address conversion information relating to data to be addressed in the nonvolatile memory. Based on whether first processing is performed on the nonvolatile memory or second processing is performed on the nonvolatile memory, the processor controls to store whether the logical-to-physical address conversion information relating to the first processing to be in the primary cache memory as cache data or logical-to-physical address conversion information relating to the second processing to be in the secondary cache memory as cache data.

公开(公告)号：US11704234B2

公开(公告)日：2023-07-18

申请号：US16860093

申请日：2020-04-28

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F12/02 ,  G11C16/28 ,  G11C16/08 ,  G11C16/04 ,  G06F3/06 ,  G06F9/4401

CPC classification number: G06F12/0246 ,  G06F3/064 ,  G06F3/0608 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4401 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/28 ,  G06F2212/7201

Abstract: The present invention provides a method for accessing a flash memory module is disclosed, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of block, each block is implemented by a plurality of word lines, each word line corresponds to K pages, and each word line includes a plurality of memory cells supporting a plurality of states, and the method includes the steps of: receiving data from a host device; generating dummy data; and writing the data with the dummy data to a plurality of specific blocks, wherein for each of a portion of the word lines of the specific blocks, the dummy data is written into at least one of the K pages, and the data from the host device is written into the other page(s) of the K pages.

公开(公告)号：US11698856B2

公开(公告)日：2023-07-11

申请号：US17480835

申请日：2021-09-21

Applicant: Micron Technology, Inc.

Inventor： Antonio David Bianco

IPC: G06F12/02 ,  G06F12/0868 ,  G06F9/38 ,  G06F12/0891

CPC classification number: G06F12/0246 ,  G06F9/3836 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/7201

Abstract: Methods, systems, and devices for maintaining sequentiality for media management of a memory sub-system are described. A plurality of read commands in connection with a set of media management operations for a plurality of transfer units are issued according to a read sequence. A plurality of entries associated with the set of media management operations are stored. A plurality of write commands in connection with the set of media management operations are issued based on the plurality of entries of the read sequence.

公开(公告)号：US20230214332A1

公开(公告)日：2023-07-06

申请号：US18097429

申请日：2023-01-16

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  Jonathan Scott Parry

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/1408 ,  G06F12/0292 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.

公开(公告)号：US11687443B2

公开(公告)日：2023-06-27

申请号：US17159327

申请日：2021-01-27

Applicant: EMC IP Holding Company LLC

Inventor： Owen Martin ,  Michael Scharland ,  Earl Medeiros ,  Parmeshwr Prasad

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/0873 ,  G06F12/1045

CPC classification number: G06F12/0238 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0689 ,  G06F12/0873 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/7201

Abstract: The present disclosure relates to one or more memory management techniques. In embodiments, one or more regions of storage class memory (SCM) of a storage array is provisioned as expanded global memory. The one or more regions can correspond to SCM persistent cache memory regions. The storage array's global memory and expanded global memory can be used to execute one or more storage-related services connected to servicing (e.g., executing) an input/output (IO) operation.