Abstract:
An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.
Abstract:
A High Definition Multi-Media Interface (HDMI) cable may exhibit frequency dependent signal attenuation, inter symbol interference, and inter-pair skew. A boost device integrated with the cable can compensate for such impairments of the cable. A self calibrating cable with a boost device of the embodiment of the invention is described, in which parameters that control the response of the boost device are set optimally in a self-calibrating process comprising looping the boosted cable on itself through a calibration fixture that contains a calibration control device. The boost device includes pattern generators and a sampling circuit. Each high speed channel of the cable is separately tested and calibrated with the help of one of the other channels serving as a sampling channel. Additional embodiments provide for a selected replica boost device and a distinct pattern generator device in the calibration fixture.
Abstract:
A digitizing instrument is used for modifying pattern data and jitter and noise components of a communication signal. In a typical implementation, the midpoints of a rising edge slope and horizontal portion of the communication signal are determined and multiple digital data records are acquired at the midpoints. The data sample records are transformed to frequency components and the random jitter and noise, and periodic jitter and noise components are determined. A correlated pattern data and the jitter and noise components are matrix elements in a simulated signal channel having communication system elements. Each correlated pattern data and jitter and noise component may be modified for each of the communication system element. The selectively modified correlated pattern data and jitter and noise components are combined to produce a modified communication signal that is displayed as a numeric table, eye diagram or bit error rate presentation.
Abstract:
Embodiments of methods and apparatus for estimating a channel state information (CSI) and a channel quality indicator (CQI) of a frame; determining a combined CSI and a combined CQI of the frame; and transmitting the CSI and the combined CQI are disclosed. Additional variants and embodiments are also disclosed.
Abstract:
Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.
Abstract:
The invention proposes a method and apparatus for determination of transmission quality of a communication link between a transmitter and a receiver. Among others, the invention allows to determine the transmission quality of a communication link between a transmitter and a receiver by a tier device, for example a transmission quality testing or monitoring device.
Abstract:
A method and system for removing the effect of intersymbol interference (ISI) from a data record indicating times of logic level transitions exhibited by a data signal that has been distorted by ISI exhibited by a system having a particular step response may perform the following acts. The data record may be received, and a transition from within the data may be selected record for removal of ISI. Preceding transitions within the data record are then inspected. A time defect is obtained, based at least in part upon the inspected preceding transitions. Finally, the data record is adjusted, based upon the time defect, to indicate a new time of transition for the selected transition, thereby removing the effect of ISI for the selected transition.
Abstract:
An integrated circuit having a corresponding method comprises a plurality of ports to transmit and receive packets of data; a forwarding engine to transfer the packets of data between the ports; and a controller to receive one or more packet definitions that specify characteristics of a packet; and wherein at least one of the ports comprises a packet generator to originate one or more packets of data according to one or more of the packet definitions received by the controller.
Abstract:
An HDMI cable may exhibit frequency dependent signal attenuation, inter symbol interference, and inter-pair skew. A boost device integrated with the cable can compensate for such impairments of the cable. A self calibrating cable with a boost device of the embodiment of the invention is described, in which parameters that control the response of the boost device are set optimally in a self-calibrating process comprising looping the boosted cable on itself through a calibration fixture that contains a calibration control device. The boost device includes pattern generators and a sampling circuit. Each high speed channel of the cable is separately tested and calibrated with the help of one of the other channels serving as a sampling channel.
Abstract:
A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.