公开(公告)号：US20020030577A1

公开(公告)日：2002-03-14

申请号：US09951666

申请日：2001-09-12

Inventor： Akinobu Shibuya ,  Koji Matsui

IPC: H01C001/012

CPC classification number: H01C7/006 ,  H01C3/04 ,  H01C17/12 ,  H05K1/167 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2203/0361

Abstract: A thin-film resistor that enables a pattern to be simply formed by means of wet etching, that has an excellent resistance temperature characteristic, and that can be easily manufactured, and a method for manufacturing this thin-film resistor, as well as a wiring substrate with this thin-film resistor formed therein. A thin resistor film according to this invention has a structure in which crystal grains deposit in the matrix of amorphous titanium nitride. The thin resistor film is formed on a substrate. The crystal grains includes at least one of crystal titanium nitride and crystal titanium. The thin resistor film can be manufactured using a simple process and can provide a wide range of resistance values with a small tolerance and a temperature coefficient of resistance close to zero.

Abstract translation: 一种薄膜电阻器，其能够通过湿法蚀刻简单地形成图案，具有优异的电阻温度特性，并且可以容易地制造，以及制造该薄膜电阻器的方法以及布线 基板上形成有该薄膜电阻。 根据本发明的薄电阻膜具有其中晶粒沉积在非晶氮化钛基体中的结构。 薄电阻膜形成在基板上。 晶粒包括晶体氮化钛和晶体钛中的至少一种。 可以使用简单的工艺制造薄电阻膜，并且可以提供具有小公差和电阻温度系数接近于零的宽范围的电阻值。

公开(公告)号：US06356455B1

公开(公告)日：2002-03-12

申请号：US09404496

申请日：1999-09-23

Applicant: Richard W. Carpenter

Inventor： Richard W. Carpenter

IPC: H05K116

CPC classification number: H05K1/167 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0064 ,  H05K3/06 ,  H05K3/4611 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09672 ,  H05K2203/0338 ,  H05K2203/1338 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155

Abstract: A thin electrical circuitry structure is formed which contains conductive circuitry traces, integral capacitors and integral resistors. A first laminate structure comprises a conductive foil having a layer of embeddable dielectric material laminated thereto. A second laminate structure comprises a conductive foil having a layer of resistive material on one side, the thickness of the resistive material layer being less than that of the layer of embeddable dielectric material. The resistive material layer is circuitized to produce resistive patches, and the two structures are laminated together, embedding the resistive patches in the dielectric material layer. One of the foils is circuitized providing circuitry traces, optional inductor coils, and capacitor plates. That foil embedded in dielectric laminate to support the structure for further processing. The other foil is then circuitized providing circuitry traces, optional inductor coils and capacitor plates. Traces on one side connector with the resistive material patches to provide the resistors.

Abstract translation: 形成薄电路结构，其包含导电电路迹线，集成电容器和积分电阻器。 第一层压结构包括具有层压在其上的可嵌入介质材料层的导电箔。 第二层压结构包括在一侧具有电阻材料层的导电箔，电阻材料层的厚度小于可嵌入介电材料层的厚度。 电阻材料层被电路化以产生电阻贴片，并且将两个结构层压在一起，将电阻贴片嵌入电介质材料层中。 其中一个箔被电路化，提供电路迹线，可选的电感线圈和电容器板。 该箔片嵌入电介质层压板中以支撑结构进行进一步处理。 然后将另一片电路电路化，提供电路迹线，可选的电感线圈和电容器板。 在一侧连接器上跟踪电阻材料贴片以提供电阻。

公开(公告)号：US20020013997A1

公开(公告)日：2002-02-07

申请号：US09957747

申请日：2001-09-21

Inventor： Gregory J. Dunn ,  Min-Xian Zhang ,  Jovica Savic

IPC: H01C017/06 ,  H01C017/00

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2203/0361 ,  H05K2203/0723 ,  H05K2203/1453 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/4913

Abstract: Printed circuit boards with integral high and low value resistors are efficiently produced. The method of their manufacture entails applying a first layer of a low resistance material onto a dielectric substrate in a predetermined thickness and pattern. The pattern defines the electrical lengths and widths of low value resistors, as well as pairs of terminal electrode pads for the high value resistors. A second layer of a high resistance material is applied between and in contact with the top surfaces of the facing ends of each member of the terminal pad pairs. The fixed lengths, widths and thicknesses of the patterned high resistance material determine the values of the high value resistors. Conductive metal terminals are provided at the ends of the low value resistors and at the distal ends of the high value resistor pad pairs to complete the resistors.

Abstract translation: 具有集成高，低值电阻器的印刷电路板得到有效的生产。 其制造方法需要以预定的厚度和图案将第一层低电阻材料施加到电介质基板上。 该模式定义了低值电阻器的电气长度和宽度，以及用于高值电阻器的一对端子电极焊盘。 将高电阻材料的第二层施加在端子垫对的每个构件的面对端的顶表面之间并与之接触。 图案化高电阻材料的固定长度，宽度和厚度决定了高值电阻器的值。 导电金属端子设置在低值电阻的两端，并在高电阻焊盘对的末端设置，以完成电阻。

公开(公告)号：US20020011596A1

公开(公告)日：2002-01-31

申请号：US09870415

申请日：2001-05-29

Inventor： Akiyuki Yoshisato ,  Kazuhiko Ueda ,  Yasuhiro Ikarashi ,  Akihiko Inoue ,  Hiroshi Sakuma

IPC: H01L031/112 ,  H01L031/036 ,  H01L029/76

CPC classification number: H05K3/403 ,  H01L23/647 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/16 ,  H05K3/246 ,  H05K2201/0317 ,  H05K2201/0347 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: The invention provides a surface mounting type electronic circuit unit that is suitable for miniaturization and is suitable for simple output adjustment. Circuit elements including capacitors, resistors, and inductance elements and a conducting pattern connected to the circuit elements are formed on an alumina substrate by means of thin film forming technique, and a diode D1 and a semiconductor chip of a transistor are fixed to a connection land of the conducting pattern by means of wire bonding, wherein only the emitter resistor out of the base bias voltage dividing resistors and the emitter resistor of the transistor is trimmed for output adjustment.

Abstract translation: 本发明提供一种适合小型化的表面安装型电子电路单元，适用于简单的输出调整。 通过薄膜形成技术在氧化铝基板上形成包括电容器，电阻器和电感元件的电路元件和连接到电路元件的导电图案，并且将二极管D1和晶体管的半导体芯片固定到连接区域 的导线图案，其中仅偏压基极偏压分压电阻器中的发射极电阻器和晶体管的发射极电阻器被修整以用于输出调节。

公开(公告)号：US20020003261A1

公开(公告)日：2002-01-10

申请号：US09898670

申请日：2001-07-02

Applicant: Alps Electric Co., Ltd.

Inventor： Shinji Murata ,  Ken Yamamura ,  Mitsuru Tokuta

IPC: H01L023/62 ,  H01L029/00 ,  H01L023/495

CPC classification number: H01L28/40 ,  H01L2224/4813 ,  H01L2924/19107 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/386 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2201/09909

Abstract: In order to provide an electronic circuit board capable of preventing the breakdown voltage of a capacitor element from dropping and excellent in high frequency performance, a positive type photoresist is spin-coated over the surface of an alumina substrate and is exposed to light and developed to form an insulating layer partially, followed by formation of a capacitor element by successively stacking a lower electrode, a dielectric layer and an upper electrode over this insulating layer, further followed by formation of a resistance element, an inductor element and a transmission line, each in a filmy state, over the surface of the alumina substrate.

Abstract translation: 为了提供能够防止电容器元件的击穿电压下降且高频性能优异的电子电路板，将正型光致抗蚀剂旋涂在氧化铝基板的表面上并暴露于光并显影至 形成绝缘层，接着通过在该绝缘层上依次层叠下电极，电介质层和上电极而形成电容器元件，然后形成电阻元件，电感器元件和传输线，每个 在薄膜状态下，在氧化铝基底的表面上。

公开(公告)号：US06232047B1

公开(公告)日：2001-05-15

申请号：US09261093

申请日：1999-03-02

Applicant: Robert Charles Frye ,  Yee Leng Low ,  King Lien Tai

Inventor： Robert Charles Frye ,  Yee Leng Low ,  King Lien Tai

IPC: G03C500

CPC classification number: H05K3/246 ,  H01P11/003 ,  H05K1/0242 ,  H05K3/146 ,  H05K2201/0317

Abstract: The specification describes method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip at the edge of the conductive strip.

Abstract translation: 该说明书描述了用于改善由厚膜糊技术形成的导电金属条的边缘敏锐度的方法。 实现了使用厚膜技术形成的条的体积特性的优点，同时利用在导电条的边缘处的薄膜修剪带克服了差的边缘限定的缺点。

公开(公告)号：US06212078B1

公开(公告)日：2001-04-03

申请号：US09427767

申请日：1999-10-27

Applicant: Andrew T. Hunt ,  Wen-Yi Lin ,  Richard W. Carpenter

Inventor： Andrew T. Hunt ,  Wen-Yi Lin ,  Richard W. Carpenter

IPC: H05K111

CPC classification number: H05K1/162 ,  H05K1/167 ,  H05K3/4623 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0338 ,  H05K2203/1338 ,  Y10T428/24917

Abstract: Nanolaminates are formed by alternating deposition, e.g., by combustion chemical vapor deposition (CCVD), layers of resistive material and layers of dielectric material. Outer resistive material layers are patterned to form discrete patches of resistive material. Electrical pathways between opposed patches of resistive material on opposite sides of the laminate act as capacitors. Electrical pathways horizontally through resistive material layers, which may be connected by via plated holes, act as resistors.

Abstract translation: 通过交替沉积，例如通过燃烧化学气相沉积（CCVD），电阻材料层和电介质材料层形成纳米级氨酸盐。 外部电阻材料层被图案化以形成电阻材料的离散贴片。 在层压板相对两侧的相对电阻材料片之间的电气通路用作电容器。 通过可通过电镀孔连接的电阻材料层的电路径用作电阻。

公开(公告)号：US6136047A

公开(公告)日：2000-10-24

申请号：US222316

申请日：1998-12-29

Applicant: Kazuaki Karasawa ,  Teru Nakanishi ,  Toshiya Akamatsu

Inventor： Kazuaki Karasawa ,  Teru Nakanishi ,  Toshiya Akamatsu

IPC: H01L21/60 ,  H05K3/04 ,  H05K3/34 ,  H01L23/48 ,  H01L21/00 ,  H01L21/64 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/12 ,  H01L24/11 ,  H01L24/17 ,  H05K3/3457 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/1143 ,  H01L2224/11849 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/1701 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H05K2201/0317 ,  H05K2203/0338 ,  H05K3/048 ,  Y10T29/41

Abstract: A solder bump transfer plate having a plurality of solder deposits on the surface non-wettable to molten solder both diameter and spacing of which are both smaller than diameter and spacing of the terminal pads on a semiconductor substrate.

Abstract translation: 一种焊料凸块传递板，其具有在不能润湿熔融焊料的表面上的多个焊料沉积物，其两个直径和间距均小于半导体衬底上的端子焊盘的直径和间距。

公开(公告)号：US6117784A

公开(公告)日：2000-09-12

申请号：US968189

申请日：1997-11-12

Applicant: Cyprian Emeka Uzoh

Inventor： Cyprian Emeka Uzoh

IPC: C23C18/31 ,  H01L21/285 ,  H01L21/288 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H05K3/06 ,  H05K3/10 ,  H01L21/311

CPC classification number: H05K3/108 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L2924/0002 ,  H05K2201/0317 ,  H05K3/067

Abstract: Metal wiring is provided in an integrated circuit by sputter coating onto a semiconductor substrate a copper seed layer; depositing and patterning a photoresist; electroplating or electrolessly plating a metal within the openings of the photoresist; stripping the remaining photoresist; and etching the copper seed layer with an etchant that preferentially etches the copper seed layer at a rate higher than that for the electroplated or electrolessly plated metal.

Abstract translation: 通过在半导体衬底上溅射涂覆铜籽晶层，在集成电路中提供金属布线; 沉积和图案化光致抗蚀剂; 在光致抗蚀剂的开口内电镀或无电镀金属; 剥离剩余的光刻胶; 并用蚀刻剂蚀刻铜籽晶层，所述蚀刻剂优先以高于电镀或无电镀金属的速率蚀刻铜籽晶层。

公开(公告)号：US6007652A

公开(公告)日：1999-12-28

申请号：US26208

申请日：1993-03-02

Applicant: Takao Hosokawa ,  Yoshiaki Kohno

Inventor： Takao Hosokawa ,  Yoshiaki Kohno

IPC: H01G4/005 ,  H05K3/20

CPC classification number: H01G4/005 ,  H05K3/20 ,  H05K3/205 ,  H05K2201/0317 ,  H05K2203/0156

Abstract: A metal thin film having excellent transferability onto a ceramic sheet is provided in order to facilitate formation of an internal electrode for a multilayer ceramic capacitor, for example, by a technique of transferring a metal thin film. A first metal layer (2) of nickel or copper or another metal is formed on a film (1) by vapor deposition, and then a second metal layer (3) of nickel or copper or another metal is formed on the first metal layer (2) by wet plating such as electroplating or electroless plating, thereby providing a metal thin film constituted by the first and second metal layers (2 and 3) having excellent transferability.

Abstract translation: 提供了具有优异的陶瓷片转印性的金属薄膜，以便于例如通过转印金属薄膜的技术形成多层陶瓷电容器的内部电极。 通过气相沉积在膜（1）上形成镍或铜或其他金属的第一金属层（2），然后在第一金属层上形成镍或铜或其他金属的第二金属层（3） 2）通过电镀或化学镀等湿法镀覆，由此提供由具有优异转印性的第一和第二金属层（2和3）构成的金属薄膜。