公开(公告)号：US08246201B2

公开(公告)日：2012-08-21

申请号：US11813857

申请日：2006-01-16

Applicant: Pierre-Alain Dumas

Inventor： Pierre-Alain Dumas

IPC: F21S4/00

CPC classification number: H05K1/18 ,  H05K1/0209 ,  H05K3/281 ,  H05K3/3447 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/062 ,  H05K2201/09363 ,  H05K2201/10106

Abstract: The invention relates to a specific printed circuit (7) comprising independent etched blocks (4) or segments in series of four such that, on a series circuit comprising five LEDs, the four blocks serve as the positioning and connection points for the welding of the pins of the LEDs, said pins being welded in an anode-to-cathode series, or the reverse depending on the direction of the current, i.e. eight electrodes in isolated blocks, such as to ensure that the connection is powered and the LEDs are fixed correctly in series of five. According to the invention, the square or rectangular blocks have a large surface (2) such that the successive holes do not tear the film of epoxy copper. In addition, said blocks are disposed along a path and a successive diagram (21) defines the symbol or pattern to be represented by the LEDs (12) which are disposed and aligned on the other decorated face of the epoxy. The incoming or outgoing bases, which supply the positive (20) or negative (3) power, or the opposite depending on the direction of the LEDs, can comprise the outgoing or incoming base that is common to other series, by means of suitable etching. The negative is always at the center of the pattern. The circuit is divided into three connection zones, A, B, C, and is powered by external contact springs. The invention is intended for the series powering of a longilineal distribution of five LEDs in series, or a multiple thereof.

Abstract translation: 本发明涉及一种特定的印刷电路（7），其包括独立的蚀刻块（4）或四个串联的段，使得在包括五个LED的串联电路上，四个块用作焊接的定位和连接点 LED的引脚，所述引脚以阳极至阴极串联焊接，或者反向取决于电流的方向，即隔离块中的八个电极，以确保连接被供电，并且LED固定 正确的五个系列。 根据本发明，正方形或矩形块具有大的表面（2），使得连续的孔不会撕裂环氧铜的膜。 此外，所述块沿着路径设置，并且连续图（21）限定由LED（12）表示的符号或图案，其被布置并对准在环氧树脂的另一装饰面上。 根据LED的方向提供正（20）或负（3）功率或相反的输入或输出基极可以通过适当的蚀刻包括其他系列共同的输出或输入基极 。 负数总是在图案的中心。 电路分为三个连接区域A，B，C，并由外部接触弹簧供电。 本发明旨在对串联的五个LED的串联分配进行串联供电，或其倍数。

公开(公告)号：US20110128100A1

公开(公告)日：2011-06-02

申请号：US12674221

申请日：2008-07-24

Applicant: Risato Ohhira

Inventor： Risato Ohhira

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/15323 ,  H01L2924/16195 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01P1/047 ,  H01P3/08 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09363 ,  H05K2201/09618 ,  H05K2201/09663 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The high-frequency wiring board of the present invention includes: first coplanar lines provided with a first signal line and a first planar ground pattern formed on the same wiring layer as the first signal line; second coplanar lines provided with a second signal line formed on a different wiring layer than the first signal line and a second planar ground pattern formed on the same wiring layer as the second signal line; and a first ground pattern formed on the same wiring layer as the first coplanar lines. The first coplanar lines and the second coplanar lines are connected. At least the first ground pattern and the first planar ground pattern are separated in a region following the second signal line from the connection of the first signal line and the second signal line.

Abstract translation: 本发明的高频布线基板包括：第一共面线，设置有与第一信号线在同一布线层上形成的第一信号线和第一平面接地图案; 第二共面线设置有形成在与第一信号线不同的布线层上的第二信号线和形成在与第二信号线相同的布线层上的第二平面接地图案; 以及形成在与第一共面线相同的布线层上的第一接地图案​​。 第一共面线和第二共面线被连接。 至少第一接地图案​​和第一平面接地图案在第二信号线之后的区域中与第一信号线和第二信号线的连接分开。

公开(公告)号：US20110103058A1

公开(公告)日：2011-05-05

申请号：US11813857

申请日：2006-01-16

Applicant: Pierre-Alain Dumas

Inventor： Pierre-Alain Dumas

IPC: F21S4/00

CPC classification number: H05K1/18 ,  H05K1/0209 ,  H05K3/281 ,  H05K3/3447 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/062 ,  H05K2201/09363 ,  H05K2201/10106

Abstract: The invention relates to a specific printed circuit (7) comprising independent etched blocks (4) or segments in series of four such that, on a series circuit comprising five LEDs, the four blocks serve as the positioning and connection points for the welding of the pins of the LEDs, said pins being welded in an anode-to-cathode series, or the reverse depending on the direction of the current, i.e. eight electrodes in isolated blocks, such as to ensure that the connection is powered and the LEDs are fixed correctly in series of five. According to the invention, the square or rectangular blocks have a large surface (2) such that the successive holes do not tear the film of epoxy copper. In addition, said blocks are disposed along a path and a successive diagram (21) defines the symbol or pattern to be represented by the LEDs (12) which are disposed and aligned on the other decorated face of the epoxy. The incoming or outgoing bases, which supply the positive (20) or negative (3) power, or the opposite depending on the direction of the LEDs, can comprise the outgoing or incoming base that is common to other series, by means of suitable etching. The negative is always at the centre of the pattern. The circuit is divided into three connection zones, A, B, C, and is powered by external contact springs. The invention is intended for the series powering of a longilineal distribution of five LEDs in series, or a multiple thereof.

Abstract translation: 本发明涉及一种特定的印刷电路（7），其包括独立的蚀刻块（4）或四个串联的段，使得在包括五个LED的串联电路上，四个块用作焊接的定位和连接点 LED的引脚，所述引脚以阳极至阴极串联焊接，或者反向取决于电流的方向，即隔离块中的八个电极，以确保连接被供电并且LED固定 正确的五个系列。 根据本发明，正方形或矩形块具有大的表面（2），使得连续的孔不会撕裂环氧铜的膜。 此外，所述块沿着路径设置，并且连续图（21）限定由LED（12）表示的符号或图案，其被布置并对准在环氧树脂的另一装饰面上。 根据LED的方向提供正（20）或负（3）功率或相反的输入或输出基极可以通过适当的蚀刻包括其他系列共同的输出或输入基极 。 负数总是在图案的中心。 电路分为三个连接区域A，B，C，并由外部接触弹簧供电。 本发明旨在对串联的五个LED的串联分配进行串联供电，或其倍数。

公开(公告)号：US07821115B2

公开(公告)日：2010-10-26

申请号：US11566892

申请日：2006-12-05

Applicant: Chihiro Sasaki ,  Yasuaki Iwata

Inventor： Chihiro Sasaki ,  Yasuaki Iwata

IPC: H01L23/495 ,  H01L21/00 ,  H01R9/00

CPC classification number: H01L23/4985 ,  H01L23/3735 ,  H01L2924/0002 ,  H05K1/0209 ,  H05K1/189 ,  H05K2201/09363 ,  H05K2201/09781 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A semiconductor device on a tape carrier package with improved heat dissipation, as provided. The number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration, and narrower pitches are employed. Included are a tape carrier 20 having lead patterns 21 to 24 formed on a tape base 28 thereof, and a semiconductor device 10 mounted on the tape carrier 20 and having electrode patterns 11 to 14 disposed thereon. The semiconductor device 10 includes heat dissipating electrode patterns 15 to 17 at positions where the heat dissipating electrode patterns 15 to 17 do not interfere with the electrode patterns 11 to 14. The lead patterns 21 to 24 are electrically connected to the corresponding electrode patterns 11 to 14, respectively. On the tape carrier 20, heat dissipation patterns 25 to 27 are formed. The heat dissipation patterns have a surface area broader than that of the lead patterns and have the heat dissipating electrode patterns disposed thereon.

Abstract translation: 如提供的，具有改善的散热性的带载体封装上的半导体器件。 为了实现多通道配置，已经增加了半导体器件的输出数量，并且采用更窄的间距。 包括形成在其基带28上的引线图案21至24以及安装在带载体20上并具有布置在其上的电极图案11至14的半导体器件10的带状载体20。 半导体装置10在散热电极图案15〜17不与电极图案11〜14不干涉的位置包括散热电极图案15〜17。引线图案21〜24电连接到对应的电极图案11〜 14。 在载带20上形成散热图案25〜27。 散热图案的表面积比引线图案宽，并且散热电极图案设置在其上。

公开(公告)号：US07749813B2

公开(公告)日：2010-07-06

申请号：US12038200

申请日：2008-02-27

Applicant: Boris Kolodin ,  James Reginelli

Inventor： Boris Kolodin ,  James Reginelli

IPC: H01L21/00 ,  H01L23/12 ,  H01L23/053 ,  H05K1/00 ,  H05K3/02 ,  H05K3/10

CPC classification number: H01L25/0753 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01079 ,  H05K3/027 ,  H05K3/064 ,  H05K2201/09363 ,  H05K2201/10106 ,  H05K2203/1476 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A packaging method comprises: forming a circuit board by forming a substantially continuous conductive layer on an insulating board and removing selected portions of the continuous conductive layer to define an electrically conductive trace; laser cutting the electrically conductive trace to define sub-traces electrically isolated from each other by a laser-cut gap formed by the laser cutting; and bonding a light emitting diode (LED) chip to the circuit board across or adjacent to the laser-cut gap, the bonding including operatively electrically connecting an electrode of the LED chip to one of the sub-traces without using an interposed submount. A semiconductor package comprises an LED chip flip-chip bonded to sub-traces of an electrically conductive trace of a circuit board, the sub-traces being electrically isolated from each other by a narrow gap of less than or about 100 microns.

Abstract translation: 封装方法包括：通过在绝缘板上形成基本上连续的导电层形成电路板，并移除所述连续导电层的选定部分以限定导电迹线; 激光切割导电迹线以通过激光切割形成的激光切割间隙来彼此电隔离的子迹线; 以及将发光二极管（LED）芯片连接到所述激光切割间隙上或与所述激光切割间隙相邻的所述电路板，所述接合包括在不使用插入的基座的情况下将所述LED芯片的电极可操作地电连接到所述子迹线之一。 半导体封装包括结合到电路板的导电迹线的子迹线的LED芯片倒装芯片，子迹线通过小于或约100微米的窄间隙彼此电隔离。

公开(公告)号：US07710045B2

公开(公告)日：2010-05-04

申请号：US11276901

申请日：2006-03-17

Applicant: John C. Schultz ,  Nelson B. O'Bryan

Inventor： John C. Schultz ,  Nelson B. O'Bryan

IPC: H05B41/16

CPC classification number: H05K1/0204 ,  F21K9/00 ,  G02F2001/133628 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/0209 ,  H05K1/0373 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/0209 ,  H05K2201/09318 ,  H05K2201/09363 ,  H05K2201/10106 ,  H05K2203/1189 ,  H01L2924/00 ,  H01L2224/4554

Abstract: Illumination assemblies include a substrate having a first and second electrically conductive layer separated by an electrically insulating layer. The insulating layer includes a polymer material loaded with thermally conductive particles. At least a portion of the thermally conductive particles simultaneously contact both the first and second electrically conductive layers. A plurality of light sources such as LEDs or other miniature light sources are preferably disposed on the first conductive layer.

Abstract translation: 照明组件包括具有由电绝缘层分隔开的第一和第二导电层的衬底。 绝缘层包括装载有导热颗粒的聚合物材料。 至少一部分导热颗粒同时接触第一和第二导电层。 诸如LED或其它微型光源的多个光源优选设置在第一导电层上。

公开(公告)号：US20090316375A1

公开(公告)日：2009-12-24

申请号：US12457219

申请日：2009-06-04

Applicant: Kouji Ueda

Inventor： Kouji Ueda

IPC: H05K7/06 ,  H05K3/34

CPC classification number: H05K3/3494 ,  H05K1/0206 ,  H05K1/0212 ,  H05K1/111 ,  H05K1/113 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09263 ,  H05K2201/09363 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/09781 ,  H05K2201/099 ,  H05K2201/10015 ,  H05K2201/1003 ,  Y02P70/611 ,  Y10T29/49144

Abstract: An electronic circuit board includes a substrate, a plurality of devices mounted on the substrate, and a pattern part disposed on a surface of the substrate. The devices include a surface mount device having a heat capacity higher than other device. The surface mount device includes a terminal part. The pattern part has an area larger than a pattern area determined in accordance with a current capacity for securing a required current value to be supplied to the surface mount device. The pattern part includes a land part to which the terminal part of the surface mount device is coupled with a solder melted by heating in a reflow furnace.

Abstract translation: 电子电路板包括基板，安装在基板上的多个装置以及设置在基板的表面上的图案部分。 这些装置包括具有高于其它装置的热容量的表面安装装置。 表面安装器件包括端子部件。 图案部分具有大于根据当前容量确定的图案区域的面积，以确保要提供给表面安装装置的所需电流值。 图案部分包括表面安装装置的端子部分与通过在回流炉中加热熔化的焊料耦合的焊盘部分。

公开(公告)号：US07271099B2

公开(公告)日：2007-09-18

申请号：US11146498

申请日：2005-06-06

Applicant: Nigel Ingram Bromley ,  Martin Philip Gouch ,  Christoph Bittner

Inventor： Nigel Ingram Bromley ,  Martin Philip Gouch ,  Christoph Bittner

IPC: H01L21/76

CPC classification number: H05K3/027 ,  H05K3/061 ,  H05K2201/09363 ,  H05K2203/013 ,  H05K2203/1476 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A method of forming a conductive pattern on a substrate. The method comprising providing a substrate carrying a conductive layer; forming a first portion of the conductive pattern by exposing the conductive layer to a laser and controlling the laser to remove conductive material around the edge(s) of desired conductive region(s) of the first portion; and laying down an etch resistant material on the conductive layer, the etch resistant material defining a second portion of the conductive pattern, removing conductive material from those areas of the second portion not covered by the etch resistant material, and then removing the etch resistant material.

Abstract translation: 在基板上形成导电图案的方法。 该方法包括提供承载导电层的衬底; 通过将所述导电层暴露于激光来形成所述导电图案的第一部分，并且控制所述激光以去除所述第一部分的所需导电区域的边缘周围的导电材料; 以及在所述导电层上铺设耐蚀刻材料，所述耐蚀刻材料限定所述导电图案的第二部分，从不被所述耐蚀刻材料覆盖的所述第二部分的那些区域去除导电材料，然后去除所述耐蚀刻材料 。

公开(公告)号：US07256490B2

公开(公告)日：2007-08-14

申请号：US11591744

申请日：2006-11-02

Applicant: Warren M. Farnworth ,  Alan G. Wood

Inventor： Warren M. Farnworth ,  Alan G. Wood

IPC: H01L23/04 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/3128 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2867 ,  H01L21/4846 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0218 ,  H05K1/113 ,  H05K3/027 ,  H05K2201/09363 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A test carrier for a semiconductor component includes a base for retaining the component, and an interconnect on the base having contacts configured to electrically engage component contacts on the component. The base includes conductors in electrical communication with the contacts on the interconnect, which are defined by grooves in a conductive layer. In addition, the conductors include first portions of the conductive layer configured for electrical transmission, which are separated from one another by second portions of the conductive layer configured for no electrical transmission. The test carrier is configured for mounting to a burn in board in electrical communication with a test circuitry configured to apply test signals through the contacts on the interconnect to the component.

公开(公告)号：US20060290374A1

公开(公告)日：2006-12-28

申请号：US11447300

申请日：2006-06-06

Applicant: David Fisher ,  Philip Heft ,  Rocco Vetro

Inventor： David Fisher ,  Philip Heft ,  Rocco Vetro

IPC: G01R31/00

CPC classification number: G09F9/33 ,  G09F9/302 ,  G09F9/3023 ,  H05K1/141 ,  H05K3/321 ,  H05K2201/09227 ,  H05K2201/09363 ,  H05K2201/10106 ,  H05K2201/2054

Abstract: An alphanumeric display includes a substrate that has top and bottom surfaces, a plurality of electrical contacts on the top surface, a plurality of light-emitting electronic devices mounted on the top surface, and a plurality of electrical pads on the bottom surface. The electrical contacts are connected to at least one light-emitting electronic device, and each of the light-emitting electronic devices is electrically connected with corresponding ones of the electrical contacts. The electrical pads are electrically connected to corresponding ones of the electrical contacts for communicating to the light-emitting electronic devices external sources of electrical power and control signals. The electrical pads on the bottom surface are arranged in a pattern to facilitate connections to the device using a conductive adhesive.

Abstract translation: 字母数字显示器包括具有顶表面和底表面的基板，顶表面上的多个电触点，安装在顶表面上的多个发光电子器件以及底表面上的多个电焊盘。 电触点连接至少一个发光电子器件，并且每个发光电子器件与相应的电触点电连接。 电焊盘电连接到对应的电触头，用于与发光电子设备的外部电源和控制信号源通信。 底表面上的电焊盘以图案布置以便于使用导电粘合剂连接到装置。