公开(公告)号：US08017874B2

公开(公告)日：2011-09-13

申请号：US12388953

申请日：2009-02-19

Applicant: Mitsuru Honjo ,  Katsutoshi Kamei

Inventor： Mitsuru Honjo ,  Katsutoshi Kamei

IPC: H05K1/00

CPC classification number: H05K1/0248 ,  G11B5/484 ,  G11B5/4853 ,  G11B5/486 ,  H05K1/0219 ,  H05K1/0224 ,  H05K1/0245 ,  H05K1/0253 ,  H05K1/056 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0969

Abstract: A first insulating layer is formed on a suspension body, and a write wiring trace is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer so as to cover the wiring trace. A write wiring trace is formed, above the write wiring trace, on the second insulating layer. A ground trace is formed on one side of the write wiring trace at a distance on the second insulating layer. A third insulating layer is formed on the second insulating layer so as to cover the wiring trace and the ground trace. An opening is formed in a region, below the write wiring trace, of the suspension body.

Abstract translation: 在悬架体上形成第一绝缘层，在第一绝缘层上形成写入布线。 在第一绝缘层上形成第二绝缘层以覆盖布线迹线。 在第二绝缘层上形成写入布线迹线上方的写入布线。 在第二绝缘层上一定距离地在写入布线迹线的一侧上形成接地迹线。 在第二绝缘层上形成第三绝缘层，以覆盖布线迹线和接地迹线。 在悬挂体的写入配线轨迹的下方的区域形成有开口部。

公开(公告)号：US20110211321A1

公开(公告)日：2011-09-01

申请号：US13124751

申请日：2009-10-28

Applicant: Akira Oikawa

Inventor： Akira Oikawa

IPC: H05K1/16 ,  H05K1/03 ,  H05K1/09 ,  H05K3/36

CPC classification number: H05K3/4635 ,  H05K1/165 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/09672

Abstract: A multilayer circuit board (1) includes resin bases (101 to 10N) stacked while placing separators (121 to 12N−1) in between, interconnect patterns (111 to 11N) respectively formed on one surface of each of the resin bases (101 to 10N), and electro-conductive bumps (201 to 20N−1) which electrically connect the interconnect patterns (111 to 11N). The resin bases (101 to 10N) and the separators (121 to 12N−1) are heat-bonded, the separators (121 to 12N−1) are composed of a first thermoplastic resin material having a first glass transition temperature, and the resin bases (101 to 10N) are composed of a second thermoplastic resin material having a second glass transition temperature higher than the first glass transition temperature.

Abstract translation: 多层电路板（1）包括在分隔件（121至12N-1）之间堆叠的树脂基座（101至10N），分别形成在每个树脂基座（101至12N-1）的一个表面上的互连图案（111至11N） 10N）和电连接布线图案（111〜11N）的导电凸块（201〜20N-1）。 树脂基（101〜10N）和隔板（121〜12N-1）进行热粘合，隔板（121〜12N-1）由具有第一玻璃化转变温度的第一热塑性树脂材料构成，树脂 碱（101〜10N）由第二玻璃化转变温度高于第一玻璃化转变温度的第二热塑性树脂材料构成。

公开(公告)号：US20110194225A1

公开(公告)日：2011-08-11

申请号：US13123262

申请日：2009-10-06

Applicant: Mina Onishi ,  Yoshimitsu Ishihara ,  Hirofumi Inoue ,  Yukihiko Azuma

Inventor： Mina Onishi ,  Yoshimitsu Ishihara ,  Hirofumi Inoue ,  Yukihiko Azuma

IPC: H05F3/00

CPC classification number: H01C7/12 ,  H01T4/10 ,  H05K1/0259 ,  H05K2201/09672 ,  H05K2201/09881

Abstract: The present invention provides an electrostatic discharge protector capable of protecting electronic circuit boards having various designs from electrostatic discharge freely, simply and easily. The electrostatic discharge protector of the present invention comprises at least three conductive members containing one pair of electrodes and the conductive members other than the electrodes, the conductive members are each disposed in such a way that the gap between one conductive member and the other conductive member has a width of 0.1 to 10 μm, an insulating member is disposed and embedded in at least one of gaps having a width of 0.1 to 10 μm which are adjacent to each conductive member and one electrode is connected to the other electrode paired with the one electrode through the insulating member and the conductive members other than electrodes.

Abstract translation: 本发明提供一种静电放电保护器，其能够简单且容易地保护具有各种设计的电子电路板免受静电放电。 本发明的静电放电保护器包括至少三个包含一对电极的导电构件和除电极之外的导电构件，导电构件各自设置成使得一个导电构件和另一个导电构件之间的间隙 具有0.1至10μm的宽度，绝缘构件设置并嵌入到与每个导电构件相邻的宽度为0.1至10μm的间隙中的至少一个中，并且一个电极连接到与该一个电极配对的另一个电极 电极通过绝缘构件和除电极之外的导电构件。

公开(公告)号：US07939930B2

公开(公告)日：2011-05-10

申请号：US11928070

申请日：2007-10-30

Applicant: Zhaoqing Chen ,  Christian Schuster

Inventor： Zhaoqing Chen ,  Christian Schuster

IPC: H01L23/48 ,  H01L23/04

CPC classification number: H01L23/5222 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

Abstract: An electrical device includes a plurality of interconnects passing through a plane. The interconnects have a longitudinal axis substantially perpendicular to the plane and including an arrangement pattern which reduces or eliminates cross-talk between nearest neighboring interconnects, wherein the interconnects include a first differentially driven signal conductor pair and at least one other signal conductor, and the arrangement includes the at least one other signal conductor disposed at a substantially same distance from each conductor of the first differentially driven signal conductor pair.

Abstract translation: 电气装置包括通过平面的多个互连件。 互连具有基本上垂直于平面的纵向轴线并且包括减少或消除最近相邻互连件之间的串扰的布置图案，其中互连包括第一差分驱动信号导体对和至少一个其它信号导体，并且布置 包括设置在与第一差分驱动信号导体对的每个导体基本相同的距离处的至少一个其它信号导体。

公开(公告)号：US20110086549A1

公开(公告)日：2011-04-14

申请号：US12969779

申请日：2010-12-16

Applicant: Jack E. Caveney ,  Masud Bolouri-Saransar

Inventor： Jack E. Caveney ,  Masud Bolouri-Saransar

IPC: H01R13/66

CPC classification number: H01R13/6461 ,  H01R13/6464 ,  H01R13/6466 ,  H01R13/66 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A communication jack having crosstalk compensation features for overall crosstalk interference reduction is disclosed. In one embodiment, the jack is configured to receive a plug to form a communication connection, and comprises jack contacts disposed in the jack, with each contact having at least a first surface and a second surface. Upon the plug being received by the jack, the plug contacts interface with the first surface of the jack contacts. The jack further includes a first capacitive coupling connected between two pairs of jack contacts to compensate for near end crosstalk, with the first capacitive coupling being connected to the pairs of jack contacts along the second surface adjacent to where the plug contacts interface with the jack contacts. A far end crosstalk compensation scheme is also set forth.

Abstract translation: 公开了一种具有用于整个串扰干扰减少的串扰补偿特征的通信插座。 在一个实施例中，千斤顶配置成接收插头以形成通信连接，并且包括设置在插座中的插座触点，每个触头具有至少第一表面和第二表面。 当插头被插座接收时，插头触点与插座触点的第一表面接触。 插座还包括连接在两对插座触点之间的第一电容耦合器，以补偿近端串扰，第一电容耦合器沿着与插座触头与插座触头相接触的第二表面连接到插座触点对 。 还提出了远端串扰补偿方案。

公开(公告)号：US07916486B2

公开(公告)日：2011-03-29

申请号：US11720120

申请日：2005-08-31

Applicant: Kozo Takahashi

Inventor： Kozo Takahashi

IPC: H05K5/20

CPC classification number: H05K1/118 ,  H01R12/592 ,  H01R12/79 ,  H05K1/117 ,  H05K2201/09672 ,  H05K2201/09781 ,  H05K2201/10386 ,  H05K2203/1572 ,  Y10S439/951

Abstract: A circuit board is connected to a connector including a connection port and contact portions located at upper and lower positions of the connection port. The contact portions face each other in the vertical direction, and each contact portion is connected electrically to the opposite contact portion. The circuit board includes a base substrate, a first wiring layer, and a second wiring layer. First terminals connected to the first wiring layer are provided on one principal surface of the base substrate, and second terminals connected to the second wiring layer are provided on the other principal surface. The first terminals and the second terminals come into contact with the contact portions and are arranged so as not to overlap each other in the vertical direction.

Abstract translation: 电路板连接到包括连接端口的连接器和位于连接端口的上部和下部位置的接触部分。 接触部分在垂直方向上彼此面对，并且每个接触部分电连接到相对的接触部分。 电路板包括基底基板，第一布线层和第二布线层。 连接到第一布线层的第一端子设置在基底基板的一个主表面上，而在第二布线层上连接的第二端子设置在另一个主表面上。 第一端子和第二端子与接触部分接触并且被布置成在垂直方向上彼此不重叠。

公开(公告)号：US20110011636A1

公开(公告)日：2011-01-20

申请号：US12654491

申请日：2009-12-22

Applicant: Kwang Jae Oh ,  Joo Yong Kim ,  Yoon Hyuck Choi

Inventor： Kwang Jae Oh ,  Joo Yong Kim ,  Yoon Hyuck Choi

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/167 ,  H05K3/4644 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2203/171 ,  Y10T29/49082 ,  Y10T29/4913 ,  Y10T29/49162

Abstract: There are provided a multilayer wiring board and a method of manufacturing the same. The multilayer wiring board according to an aspect of the invention may include: a main body having a plurality of insulting layers stacked upon each other, including a first layer provided as an inner layer and a second layer provided as an outer layer; a first resistor provided on the first layer; and a second resistor provided on the second layer, connected in parallel with the first resistor, and having a smaller area than the first resistor. The multilayer wiring board obtains a target resistance value using the first and second resistors formed on the first and second layers. The second resistor, formed on the outer layer, can have a smaller area than the first resistor. Accordingly, the usable area of the outer layer is increased to thereby reduce the size of the multilayer wiring board.

Abstract translation: 提供了一种多层布线板及其制造方法。 根据本发明的一个方面的多层布线板可以包括：主体，其具有堆叠在一起的多个绝缘层，包括设置为内层的第一层和设置为外层的第二层; 设置在第一层上的第一电阻器; 以及设置在所述第二层上的与所述第一电阻并联连接并且具有比所述第一电阻器小的面积的第二电阻器。 多层布线基板使用形成在第一层和第二层上的第一和第二电阻来获得目标电阻值。 形成在外层上的第二电阻器可以具有比第一电阻器更小的面积。 因此，增加了外层的可用面积，从而减小了多层布线板的尺寸。

公开(公告)号：US07849427B2

公开(公告)日：2010-12-07

申请号：US12021363

申请日：2008-01-29

Applicant: Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhang

Inventor： Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhang

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0237 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: An auto routing method and system provides optimized circuit routing while maintaining proper reference return paths for critical signals. Critical signal paths are auto-routed simultaneously with corresponding reference return paths, and the reference return paths can be merged into reference planes if they are adjacent to regions connected to the same reference net. The reference return paths may be in a plane adjacent to the signal path plane in the same channel, or the reference returns may be routed in adjacent channels in the same plane as the signal path. A check may be performed on endpoints of each critical signal path to determine whether a reference return via is present within a proximity tolerance of the signal path endpoints, and a reference return via placed if not.

Abstract translation: 自动路由方法和系统提供优化的电路路由，同时为关键信号保留适当的参考返回路径。 临界信号路径与对应的参考返回路径同时自动路由，并且如果参考返回路径与连接到相同参考网络的区域相邻，则它们可以合并到参考平面中。 参考返回路径可以在与相同信道中的信号路径平面相邻的平面中，或者参考返回可以在与信号路径相同的平面中的相邻信道中路由。 可以在每个关键信号路径的端点上执行检查，以确定参考返回通道是否存在于信号路径端点的接近容限内，如果不是则通过放置参考返回。

公开(公告)号：US20100261346A1

公开(公告)日：2010-10-14

申请号：US12823316

申请日：2010-06-25

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01L21/768 ,  G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括在通过空隙减少与信号承载PTH的耦合并且维持 信号路径导体。

公开(公告)号：US07813141B2

公开(公告)日：2010-10-12

申请号：US12188271

申请日：2008-08-08

Applicant: William J. Borland ,  G. Sidney Cox ,  David Ross McGregor

Inventor： William J. Borland ,  G. Sidney Cox ,  David Ross McGregor

IPC: H05K1/16

CPC classification number: H05K1/167 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0361 ,  H05K2203/1461 ,  Y10T29/435

Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode; a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0.

Abstract translation: 本发明涉及可以嵌入在印刷线路板的层内的电容/电阻装置。 嵌入器件节省了电路板表面的空间，并减少了焊接连接的数量，从而提高了可靠性。 更具体地，该装置包括第一金属箔; 第二金属箔; 由所述第一金属箔形成的第一电极; 设置在所述第一电极上的电介质; 形成在电介质上并与其相邻的电阻元件; 导电迹线 以及由所述第二金属箔形成并且设置在所述电介质上并与所述电阻元件电接触的第二电极，其中所述电介质设置在所述第一电极和所述第二电极之间，并且其中所述电介质包括介电常数小于 4.0。