公开(公告)号：US5041183A

公开(公告)日：1991-08-20

申请号：US462040

申请日：1990-01-09

Applicant: Akio Nakamura ,  Osami Hayashi ,  Hideki Tabei

Inventor： Akio Nakamura ,  Osami Hayashi ,  Hideki Tabei

IPC: H01R11/01 ,  H01R4/04 ,  H01R13/24 ,  H05K1/18 ,  H05K3/30 ,  H05K3/32 ,  H05K3/36

CPC classification number: H05K3/323 ,  H01R4/04 ,  H01R12/714 ,  H01R13/2414 ,  H05K1/181 ,  H05K2201/0129 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/1189 ,  H05K3/305 ,  H05K3/321 ,  H05K3/361 ,  Y10T156/1075 ,  Y10T29/4922

Abstract: The inventive interconnector, which is used for electrically connecting two arrays of electrodes on two circuit boards, etc., is a striped sheet composed of alternately arranged strips of an insulating adhesive hot-melt resin and strips of a conductive adhesive hot-melt resin composition. The interconnector is prepared by stacking a film of the insulating resin coated on one surface with the conductive composition, integrating the stack into an integral block and slicing the block in a plane perpendicular to the surface of the stacked films. Alternatively, the interconnector is composed of a matrix of an insulating adhesive hot-melt resin and regularly distributed spots of a conductive adhesive hot-melt resin composition. Such an interconnector can be prepared by stacking alternately numbers of the above mentioned striped sheets and sheets of the insulating adhesive hot-melt resin one on the other, integrating the stack into an integral block and slicing the block in a plane perpendicular to the running direction of the conductive strips in the conductive sheets.

Abstract translation: 用于电连接两个电路板上的两个电极阵列的本发明的互连器是由交替布置的绝缘粘合剂热熔树脂条和导电粘合剂热熔树脂组合物条 。 通过将涂覆在一个表面上的绝缘树脂的膜与导电组合物层叠，将叠层整合成整体块并在垂直于堆叠膜的表面的平面中切割块来制备互连器。 或者，互连器由绝缘粘合剂热熔树脂的基体和导电粘合剂热熔树脂组合物的规则分布的点组成。 这样的互连器可以通过将上述条形片材和绝缘粘合剂热熔树脂片材交替堆叠而制成，将堆叠整合成整体块，并在与行进方向垂直的平面中切片块 的导电片中的导电条。

公开(公告)号：US4931598A

公开(公告)日：1990-06-05

申请号：US292050

申请日：1988-12-30

Applicant: Clyde D. Calhoun ,  David C. Koskenmaki

Inventor： Clyde D. Calhoun ,  David C. Koskenmaki

IPC: H01R4/04 ,  H05K3/32

CPC classification number: H01R4/04 ,  H05K3/323 ,  H05K2201/09945 ,  H05K2201/10234 ,  H05K2203/0338

Abstract: The invention provides a sheet material adapted to make bonded electrical connection to an array of closely spaced conductive terminal pads. The material may be provided as a roll of an elongated flexible connector tape. The sheet material of the invention comprises a thin, flexible insulating substrate and a plurality of longitudinally-extending, regularly-spaced, metal conductive members. The sheet may also include an adhesive layer that may cover the conductive members or at least a portion of the conductive members may extend above the adhesive layer. The conductive members may be supported and held on the substrate or may be suspended in the adhesive, out of contact with the substrate.

Abstract translation: 本发明提供了一种片材，其适于使得与紧密间隔的导电端子焊盘的阵列的结合电连接。 材料可以被设置为细长柔性连接器带的卷。 本发明的片材包括薄的柔性绝缘基底和多个纵向延伸的规则间隔的金属导电构件。 片材还可以包括可以覆盖导电构件的粘合剂层，或者导电构件的至少一部分可以在粘合剂层的上方延伸。 导电构件可以被支撑并保持在基底上，或者可以悬挂在粘合剂中，与基底不接触。

公开(公告)号：US4361634A

公开(公告)日：1982-11-30

申请号：US7731

申请日：1979-01-30

Applicant: Robert Miller

Inventor： Robert Miller

IPC: H05K1/00 ,  H05K3/00 ,  H05K3/46 ,  G03F5/00

CPC classification number: H05K3/0002 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0298 ,  H05K2201/09945 ,  H05K2203/056 ,  H05K3/4641 ,  Y10S428/901 ,  Y10S430/152

Abstract: A multilayer printed circuit board structure and a method for generating artwork masters for the manufacture thereof. The multilayer board comprises universal internal layers of predefined circuit patterns. The internal layers include power and ground planes, and for boards having high component and circuit density, one or two signal crossover layers with short, equal-length runs oriented transversely to the runs of an adjacent outermost signal layer. Electrical interconnections between layers of the circuit board are effected by interlayer conductors such as pins or plated-through holes at predefined locations. The artwork masters for the outermost layers are generated utilizing two degrees of layout precision. A universal layout master having interconnection pads and parallel circuit runs extending across the entire surface of the board is first prepared using a high degree of precision. The universal layout master is then superposed with other layout masters including a component matrix and utilized to generate a composite artwork master having relatively short circuit runs of a second degree of precision interconnecting the parallel runs and the pads. A tool for a unique outermost layer is then reproduced from the composite artwork master utilizing an artwork master of another layer to control interlayer registration.

Abstract translation: 一种多层印刷电路板结构和用于制造艺术品主人的方法。 多层板包括预定电路图案的通用内层。 内层包括电源和接地层，对于具有高分量和电路密度的板，一个或两个信号交叉层具有横向于邻近的最外层信号层的运行的短等长的运行。 电路板层之间的电气互连通过层间导体（例如在预定位置处的引脚或电镀通孔）来实现。 使用两种布局精度生成最外层的艺术品主。 首先，使用高精度地准备具有互连焊盘和延伸穿过板的整个表面的并行电路运行的通用布局主机。 然后，通用布局主体与包括组件矩阵的其他布局主体叠加，并且用于生成具有互连平行和焊盘的第二精度的相对短路运行的复合图稿母版。 然后，使用另一层的艺术作品主体，从复合艺术品母版再现用于唯一最外层的工具，以控制层间配准。

公开(公告)号：US20180310403A1

公开(公告)日：2018-10-25

申请号：US15493680

申请日：2017-04-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chad M. Albertson ,  Eric J. Campbell ,  Nicholas J. Ollerich ,  Christopher W. Steffen

IPC: H05K1/09 ,  H05K1/18 ,  H05K3/10 ,  H05K3/14 ,  H05K3/12 ,  H05K3/18 ,  H05K3/34

CPC classification number: H05K1/112 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/146 ,  H05K3/3405 ,  H05K3/3436 ,  H05K2201/09636 ,  H05K2201/09836 ,  H05K2201/09945 ,  Y10T29/49155

Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

公开(公告)号：US09873394B2

公开(公告)日：2018-01-23

申请号：US15034446

申请日：2014-10-15

Applicant: Sumitomo Wiring Systems, Ltd ,  AutoNetworks Technologies, Ltd. ,  Sumitomo Electric Industries, Ltd.

Inventor： Yoshikazu Hachiya

IPC: H01R13/46 ,  B60R16/03 ,  H05K1/02 ,  H02G3/08 ,  B60R16/023 ,  H05K3/10 ,  H05K3/24 ,  H05K3/46

CPC classification number: B60R16/03 ,  B60R16/0239 ,  H02G3/081 ,  H02G3/088 ,  H05K1/0256 ,  H05K1/0265 ,  H05K3/103 ,  H05K3/24 ,  H05K3/4617 ,  H05K3/4626 ,  H05K2201/09063 ,  H05K2201/09945 ,  H05K2201/10272

Abstract: Provided is an electrical junction box having a novel structure capable of preventing vehicle fire after the infiltration of water without depending on a waterproofing structure of the electrical junction box. An electrical junction box includes a bus bar circuit unit obtained by arranging a plurality of bus bars including a power source-side bus bar to be connected to a power source line and a ground-side bus bar to be connected to a ground line on insulated boards. In the electrical junction box, the power source-side bus bar and the ground-side bus bar are arranged adjacent to each other, and an oxide deposition inhibiting structure is provided in exposed portions of the insulated board exposed through a gap between the power source-side bus bar and the ground-side bus bar.

公开(公告)号：US20170181276A1

公开(公告)日：2017-06-22

申请号：US15370072

申请日：2016-12-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SUSUMU SAWADA ,  YOSHIHIRO TOMITA ,  KOICHI HIRANO ,  HIDEKI OHMAE

IPC: H05K1/02 ,  H05K1/18 ,  B32B5/04 ,  B32B7/08 ,  B32B3/26 ,  B32B5/02

CPC classification number: H05K1/0283 ,  B32B3/16 ,  B32B3/266 ,  B32B5/022 ,  B32B5/024 ,  B32B5/026 ,  B32B5/028 ,  B32B5/04 ,  B32B5/06 ,  B32B7/08 ,  B32B15/082 ,  B32B15/092 ,  B32B15/095 ,  B32B15/14 ,  B32B15/18 ,  B32B15/20 ,  B32B27/06 ,  B32B27/281 ,  B32B27/308 ,  B32B27/38 ,  B32B27/40 ,  B32B2250/02 ,  B32B2250/04 ,  B32B2262/0207 ,  B32B2262/0223 ,  B32B2262/0238 ,  B32B2262/0246 ,  B32B2262/0253 ,  B32B2262/0261 ,  B32B2262/0269 ,  B32B2262/0276 ,  B32B2262/0284 ,  B32B2262/0292 ,  B32B2262/04 ,  B32B2262/062 ,  B32B2262/08 ,  B32B2262/101 ,  B32B2262/103 ,  B32B2262/105 ,  B32B2262/106 ,  B32B2262/14 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2307/306 ,  B32B2307/51 ,  B32B2307/546 ,  B32B2307/724 ,  B32B2307/732 ,  B32B2457/00 ,  H01L23/5387 ,  H05K1/0366 ,  H05K1/038 ,  H05K1/18 ,  H05K1/189 ,  H05K3/202 ,  H05K2201/0133 ,  H05K2201/029 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/09945

Abstract: A substrate is provided with: a stretchable sheet; a plurality of members located on the sheet; a plurality of strips that are stretchable, and that connect the plurality of members; and a plurality of fiber threads that sew the plurality of members and the sheet together.

公开(公告)号：US20160143174A1

公开(公告)日：2016-05-19

申请号：US14942658

申请日：2015-11-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Youngmin CHO

IPC: H05K7/06 ,  H05K1/18 ,  H05K1/14 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/181 ,  H05K3/323 ,  H05K2201/09945 ,  H05K2201/10128 ,  H05K2203/0522

Abstract: A display device includes: a substrate having a pad area; a conductive pad on the pad area; a circuit member on the conductive pad, the circuit member including a bump overlapping the conductive pad; and an anisotropic conductive film between the conductive pad and the bump, the anisotropic conductive film electrically connecting the conductive pad and the bump. The anisotropic conductive film includes: an adhesive layer; at least one conductive particle positioned within the adhesive layer; and a first guide pattern positioned at a surface of the adhesive layer adjacent to the conductive pad.

Abstract translation: 显示装置包括：具有焊盘区域的基板; 焊盘区域上的导电焊盘; 所述电路构件在所述导电焊盘上，所述电路构件包括与所述导电焊盘重叠的凸块; 以及在导电焊盘和凸块之间的各向异性导电膜，各向异性导电膜电连接导电焊盘和凸块。 各向异性导电膜包括：粘合剂层; 位于所述粘合剂层内的至少一个导电颗粒; 以及位于所述粘合剂层的与所述导电垫相邻的表面的第一引导图案。

公开(公告)号：US20140340857A1

公开(公告)日：2014-11-20

申请号：US14276413

申请日：2014-05-13

Applicant: MC10, INC.

Inventor： YUNG-YU HSU ,  JOHN WORK ,  KEVIN J. DOWLING

IPC: H05K1/02

CPC classification number: H05K1/0283 ,  A61B5/0059 ,  A61B5/6846 ,  A61B2562/164 ,  H01L23/145 ,  H01L23/5386 ,  H01L23/5387 ,  H01L2924/15791 ,  H05K1/189 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/09263 ,  H05K2201/09945

Abstract: An example stretchable device is described that includes electrical contacts and an interconnect coupling the electrical contacts. The interconnect has a meander-shaped configuration that includes at least one nested serpentine-shaped feature. The interconnect can be conductive or non-conductive. The meander-shaped configuration can be a serpentine structure, providing a serpentine-in-serpentine configuration.

Abstract translation: 描述了一个示例性可拉伸装置，其包括电触点和耦合电触点的互连。 互连具有曲折形状，其包括至少一个嵌套蛇形特征。 互连可以是导电的或不导电的。 弯曲形状的构造可以是蛇形结构，提供蛇形蛇形结构。

公开(公告)号：US20140027169A1

公开(公告)日：2014-01-30

申请号：US13723156

申请日：2012-12-20

Applicant: BENQ MATERIALS CORPORATION

Inventor： Chien-Huang HUANG ,  Chen-Kuan KUO ,  Lung-Hai WU

IPC: H05K1/09

CPC classification number: H05K1/09 ,  H05K3/323 ,  H05K2201/09909 ,  H05K2201/09945 ,  H05K2203/0156 ,  H05K2203/0415

Abstract: An anisotropic conductive film is disclosed. The anisotropic conductive film includes a substrate, a plurality of insulating resin walls on the substrate and conductive materials. Each insulating resin wall is disposed on the substrate in parallel to each other. The conductive materials are arranged between the insulating resin walls and have conductivity along a direction parallel to the insulating resin walls.

Abstract translation: 公开了各向异性导电膜。 各向异性导电膜包括基板，基板上的多个绝缘树脂壁和导电材料。 每个绝缘树脂壁彼此平行地设置在基板上。 导电材料布置在绝缘树脂壁之间，并且沿着与绝缘树脂壁平行的方向具有导电性。

公开(公告)号：US08362369B2

公开(公告)日：2013-01-29

申请号：US12792334

申请日：2010-06-02

Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Masao Nakazawa

Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Masao Nakazawa

IPC: H05K1/11

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K1/0287 ,  H05K1/0306 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/09609 ,  H05K2201/09945 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A wiring board includes a core substrate having a structure including an insulating base material and a large number of filamentous conductors densely provided in the insulating base material and piercing the insulating base material in a thickness direction thereof. Pads made of portions of wiring layers are oppositely disposed on both surfaces of the core substrate and electrically connected to opposite ends of a plurality of filamentous conductors in such a manner that the pads share the filamentous conductors. A wiring connection between one surface side and the other surface side of the core substrate is made through the pads. The insulating base material is made of an inorganic dielectric. Pads made of portions of the wiring layers are disposed on both surfaces of the core substrate and electrically connected only to corresponding one end sides of different groups each formed of a plurality of filamentous conductors.

Abstract translation: 布线基板包括芯基板，该芯基板具有密封地设置在绝缘基材中的绝缘基材和大量丝状导体，并且在其厚度方向上刺穿绝缘基材。 由布线层部分构成的垫相对地设置在芯基板的两个表面上，并且以多个丝状导体的相对端电连接，使得焊盘共享丝状导体。 通过焊盘制造芯基板的一个表面侧和另一个表面侧之间的布线连接。 绝缘基材由无机电介质制成。 由布线层的一部分制成的垫片设置在芯基板的两个表面上，并且仅电连接到由多个丝状导体形成的不同组的相应一端侧。