公开(公告)号：US20040001327A1

公开(公告)日：2004-01-01

申请号：US10452455

申请日：2003-06-03

Inventor： Kazuyuki Nagata

IPC: H05K007/02 ,  H05K007/06 ,  H05K007/08 ,  H05K007/10

CPC classification number: H05K1/0266 ,  H05K1/0295 ,  H05K1/18 ,  H05K2201/09936 ,  H05K2201/09954 ,  H05K2201/10015 ,  H05K2201/10174 ,  H05K2201/10204 ,  H05K2201/10522 ,  H05K2203/168

Abstract: Disclosed is a foolproof polarity indication of poled electronics parts or devices to be given to a printed circuit board to assure that poled electronics parts and/or devices be correctly mounted in respect of their polarities to meet occasional requirements dependent on different specifications. Each pair of terminal holes are allotted to a given poled electronics part or device. Two symbols representative of such electronics part or device are arranged side by side on either side of the line drawn from one to the other terminal hole. The poled electronics part or device symbols are of reversed polarities. This dual symbol arrangement is effective to draw workers' attention in mounting electrode components in terms of their polarities. When extra components or dummy ones are combined with such a poled component, they are encircled by a boundary line, thereby showing the correct polarity direction of the poled component in respect of whether it is enclosed or not.

Abstract translation: 公开了一种给予印刷电路板的极化电子部件或装置的绝对极性指示，以确保极化的电子部件和/或设备在其极性方面被正确地安装，以满足取决于不同规格的偶尔要求。 每对端子孔分配给给定的极化电子部件或器件。 代表这种电子部件或装置的两个符号被并排地布置在从一个端子孔到另一个端子孔的线的任一侧上。 极化的电子部件或器件符号具有相反的极性。 这种双重符号排列是有效的吸引工作人员注意安装电极组件的极性方面。 当额外的元件或虚拟元件与这种极化元件组合时，它们被边界线包围，从而显示极限元件的正确极性方向是否被封闭。

公开(公告)号：US06667561B2

公开(公告)日：2003-12-23

申请号：US10063036

申请日：2002-03-13

Applicant: David Stuart Baker

Inventor： David Stuart Baker

IPC: H01L2348

CPC classification number: H05K3/303 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/029 ,  H05K1/0295 ,  H05K3/306 ,  H05K2201/09954 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49139 ,  Y10T29/49169 ,  Y10T29/49208 ,  H01L2924/00

Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

Abstract translation: 提供能够以多个插入方向操作的集成电路设计。 具体地，本发明的电路设计包括集成电路封装，其具有从集成电路封装延伸并且对称地布置的多个接触元件，以使集成电路能够以至少两个离散取向插入电路板上。 多个接触元件被指定为定位销，所述定向销布置成使得在集成电路封装上电时，定向销将指示集成电路封装在电路板中的插入取向的取向信号传送。 提供多个多路复用器装置用于响应于来自定向销的取向信号在接触元件和集成电路功能电路之间路由信号。

公开(公告)号：US20030141585A1

公开(公告)日：2003-07-31

申请号：US10064426

申请日：2002-07-12

Inventor： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC: H01L021/44

CPC classification number: H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer. Since the preferred embodiment of the present invention provides more flexibility in the placement design, a layout structure that supports the Pentium IV CPUs of different package techniques can be designed on the motherboard of the 4 layers stack structure, and these two CPUs can be supported by the same control chip.

Abstract translation: 支持两种不同包装技术的中央处理单元（CPU）的布局结构，包括包括布局结构和布局方法的主板。 根据本发明的优选实施例的布局结构从上到下顺序地在CPU的信号区域中放置顶层信号层，接地层，具有接地电位的功率层和底部焊料层 耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。 因此，耦合到控制芯片的CPU的部分信号可以放置在底部焊料层上。 由于本发明的优选实施例在布局设计中提供了更多的灵活性，因此可以在四层堆栈结构的主板上设计支持不同封装技术的Pentium IV CPU的布局结构，并且这两个CPU可以由 相同的控制芯片。

公开(公告)号：US06528734B2

公开(公告)日：2003-03-04

申请号：US10113509

申请日：2002-04-01

Applicant: Harumi Mizunashi

Inventor： Harumi Mizunashi

IPC: H05K116

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/0295 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09954 ,  H05K2201/10674 ,  Y10T29/49126 ,  H01L2224/0401

Abstract: A packaged semiconductor device comprises a packaging substrate having a core substrate having core wiring layers formed on opposite surfaces thereof, respectively, and a plurality of core via holes in the core substrate for mutually electrically connecting the core wiring layers formed on the opposite surfaces of the core substrate. Upper and lower buildup layers, each having a wiring layer, are formed on an upper surface and a lower surface of the core substrate, respectively. A semiconductor device chip is mounted on mounting pads formed on the upper buildup layer, and externally connecting electrodes are formed on the lower buildup layer. The position of the core via holes in the core substrate is standardized, regardless of the size of semiconductor device chip to be mounted. When a semiconductor device chip having a different chip size, the mounting pads formed on the upper buildup layer are located to coincide connection terminals of the semiconductor device chip of the different kind to be mounted.

公开(公告)号：US06454585B1

公开(公告)日：2002-09-24

申请号：US09920233

申请日：2001-08-01

Applicant: Steven S. Homer ,  Lee Atkinson ,  Rahul V. Lakdawala

Inventor： Steven S. Homer ,  Lee Atkinson ,  Rahul V. Lakdawala

IPC: H01R2700

CPC classification number: H05K1/117 ,  H01R27/00 ,  H01R31/08 ,  H05K1/0295 ,  H05K2201/09954 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49169 ,  Y10T29/49204 ,  Y10T29/49208

Abstract: A connection technique for switchably and mutually exclusively coupling a plurality of device sets. The connection technique utilizes a low profile connector having multiple circuit sets, each of which is configured for mutually exclusive and removable insertion into a receptacle coupled to multiple devices. Each one of the multiple circuit sets, which is inserted into the receptacle, couples a desired set of the plurality of device sets.

Abstract translation: 一种用于可互换地并且互相独立地耦合多个设备组的连接技术。 连接技术使用具有多个电路组的低轮廓连接器，每个电路组被配置为互相排斥并且可移除地插入耦合到多个装置的插座中。 插入到插座中的多个电路组中的每一个耦合多个设备组的期望集合。

公开(公告)号：US20020014949A1

公开(公告)日：2002-02-07

申请号：US09956132

申请日：2001-09-20

Applicant: TAIYO YUDEN CO., LTD

Inventor： Hirotoshi Tanaka ,  Masataka Kohara ,  Hideya Maki

IPC: H01C001/012

CPC classification number: H05K3/303 ,  H01C1/02 ,  H01C17/006 ,  H05K1/0269 ,  H05K2201/09954 ,  H05K2201/10636 ,  H05K2203/161 ,  H05K2203/168 ,  Y02P70/611 ,  Y02P70/613

Abstract: A chip component such as chip resistor, which is capable of being mounted obversely or reversely to a substrate or the like. Since the color of the armor is adjusted so as to be green identical with that of a ceramics chip, the lightness distribution of the component front face is similar with that of the component back face. Therefore, there is no case that chip component mounted obversely and chip component mounted reversely are identified as different components in a testing step of detecting a positional deviation or unloaded component by a color or monochromatic image processing (digital image processing), even if the component is mounted reversely to a substrate or the like.

Abstract translation: 诸如片状电阻器的芯片组件，其能够与衬底等相反地或相反地安装。 由于将装甲的颜色调整为与陶瓷芯片相同的绿色，所以部件正面的亮度分布与部件背面的亮度分布相同。 因此，在通过彩色或单色图像处理（数字图像处理）检测位置偏离或卸载成分的测试步骤中，即使该组件 反向安装在基板等上。

公开(公告)号：US20010033203A1

公开(公告)日：2001-10-25

申请号：US09817482

申请日：2001-03-26

Inventor： Shinji Goma ,  Masao Uno

IPC: H03B005/18

CPC classification number: H05K1/0237 ,  H03B5/1847 ,  H05K1/0231 ,  H05K1/0295 ,  H05K1/181 ,  H05K2201/09954 ,  H05K2201/10075 ,  H05K2201/10166 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A miniaturized oscillator that is manufactured with greatly reduced production time and cost includes transmission lines defining resonance circuits provided on a circuit assembly board. In this state, the impedance of each transmission line is measured. Then, according to the transmission line impedance, chip components having impedances necessary to obtain a predetermined frequency are selected and mounted on the circuit substrate. With this arrangement and method of formation, the resulting oscillator oscillates at the desired oscillation frequency and it is not necessary to trim the transmission lines in order to achieve this result. Since the oscillator does not require time to make frequency adjustments and does require use of a trimming apparatus, no deterioration in the electric characteristics due to laser trimming occurs. In addition, it is unnecessary to provide an electrode land for making frequency adjustments. As a result, the entire oscillator is miniaturized.

Abstract translation: 以大大减少的生产时间和成本制造的小型化振荡器包括限定设置在电路组装板上的谐振电路的传输线。 在这种状态下，测量每条传输线的阻抗。 然后，根据传输线阻抗，选择具有获得预定频率所需的阻抗的芯片组件并安装在电路基板上。 利用这种形成方法和方法，所得到的振荡器以期望的振荡频率振荡，为了实现该结果，不需要修整传输线。 由于振荡器不需要时间来进行频率调整，并且需要使用修整装置，所以不会发生由于激光微调造成的电特性的劣化。 此外，不需要设置用于进行频率调节的电极焊盘。 结果，整个振荡器被小型化。

公开(公告)号：US06303875B1

公开(公告)日：2001-10-16

申请号：US09236441

申请日：1999-01-25

Applicant: Shoichi Hata

Inventor： Shoichi Hata

IPC: H05K116

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0295 ,  H05K1/116 ,  H05K2201/0979 ,  H05K2201/09954 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: There are provided IC packages which eliminate the need for preparing a plurality of wiring boards even when different types of IC packages are used and a circuit device using the same. A 128-pin package is arranged, so as to output the same signal from two pins positioned on both ends of each edge thereof and wires of a wiring board corresponding to those pins are short-circuited.

Abstract translation: 提供IC封装，即使在使用不同类型的IC封装时也不需要制备多个布线板，以及使用该封装的电路装置。 布置了128引脚封装，以便从位于其每个边缘的两端的两个引脚输出相同的信号，并且与这些引脚相对应的布线板的引线短路。

公开(公告)号：US6135780A

公开(公告)日：2000-10-24

申请号：US443261

申请日：1999-11-22

Applicant: H. Edward Kelwaski ,  Robert D. Dannenberg

Inventor： H. Edward Kelwaski ,  Robert D. Dannenberg

IPC: H01R33/18 ,  H01R33/88 ,  H05K1/00 ,  H05K1/11 ,  H05K1/18 ,  H01R12/00

CPC classification number: H01R33/88 ,  H01R33/18 ,  H05K1/0295 ,  H05K1/11 ,  H05K1/182 ,  H05K2201/09954 ,  H05K2201/10325

Abstract: Two lamp sockets (40, 42) on a wiring board (32) behind a switch assembly (18) have identical geometries. Each comprises a through-hole with a polarizing feature. Plural discrete contact pads (44, 46, 48, 50) are disposed on the board surface spaced apart around the margin of each through-hole. Plural discrete conductor traces (52, 54, 56, 58) are printed on the board surface to run from the respective contact pads. Each socket can accept either a first model (66) or a second model (68) of lamp assembly to make either socket a status indicator for the switch assembly or a nighttime illumination socket. A common wiring board can thereby serve different requirements for the locations of status indicator and nighttime illumination lamps.

Abstract translation: 开关组件（18）后面的布线板（32）上的两个灯插座（40,42）具有相同的几何形状。 每个都包括具有偏振特征的通孔。 多个分立的接触垫（44,46,48,50）设置在围绕每个通孔的边缘间隔开的板表面上。 多个分立导体迹线（52,54,56,58）印刷在电路板表面上以从相应的接触焊盘运行。 每个插座可以接受灯组件的第一型号（66）或第二型号（68），以使插座成为开关组件或夜间照明插座的状态指示器。 因此，通常的布线板可以对状态指示灯和夜间照明灯的位置提供不同的要求。

公开(公告)号：US6126452A

公开(公告)日：2000-10-03

申请号：US964310

申请日：1997-11-04

Applicant: Robert-Jan Grotenhuis

Inventor： Robert-Jan Grotenhuis

IPC: H05K1/11 ,  H05K7/14 ,  H01R12/00

CPC classification number: H05K7/1422 ,  H05K1/117 ,  H05K1/0295 ,  H05K2201/09227 ,  H05K2201/09954

Abstract: Disclosed is a video card (120) which comprises a substantially rectangular, sheetlike component support(29) with a lower edge (21) and a rear edge (22). The video card (120) has a first edge connector (25) formed as a projecting portion (23) starting from the lower edge (21) of the component support (29), which projecting portion (23) is provided with terminals (24). The video card (120) further has a sub-D connector (26) provided with terminals (28), arranged at the rear edge (22) of the component support (29). According to the present invention, the video card (120) further has a second edge connector (130) formed as a projecting portion (131) starting from the lower edge (21) of the component support (29), which projecting portion (131) is provided with terminals (132), and the terminals (28) of the sub-D connector (26) are coupled to terminals (132) of the second edge connector (130).

Abstract translation: 公开了一种视频卡（120），其包括具有下边缘（21）和后边缘（22）的大致矩形的片状部件支撑件（29）。 视频卡（120）具有从部件支撑件（29）的下边缘（21）开始形成为突出部分（23）的第一边缘连接器（25），该突出部分（23）设置有端子（24） ）。 视频卡（120）还具有设置在部件支撑件（29）的后边缘（22）处的端子（28）的副D连接器（26）。 根据本发明，视频卡（120）还具有从部件支撑件（29）的下边缘（21）开始形成为突出部分（131）的第二边缘连接器（130），该突出部分 ）设置有端子（132），并且副D连接器（26）的端子（28）联接到第二边缘连接器（130）的端子（132）。