公开(公告)号：US09354975B2

公开(公告)日：2016-05-31

申请号：US14236270

申请日：2013-03-15

Applicant: EMC Corporation

Inventor： Artem Alexandrovich Aliev ,  Peter Vladimirovich Trifonov ,  Vera Dmitriyevna Miloslavskaya ,  Alexander Nicholaevich Alexeev

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/15 ,  H03M13/03 ,  H03M13/00 ,  G06F11/08

CPC classification number: G06F11/1096 ,  G06F11/085 ,  H03M13/036 ,  H03M13/15 ,  H03M13/611 ,  H03M13/616

Abstract: An improved technique involves assigning a different generator matrix to each data stripe of the redundant disk array such that all of the different generator matrices represent the same code. For example, when a k×n generator matrix G represents a linear code C, k being the block length and n the code length, then for any invertible k×k matrix P, the matrix G′=PG is also a generator that represents C. When C is a systematic code, then G consists of a k×k identity matrix representing payload data concatenated with a k×(n−k) parity matrix representing parity data. Certain matrices P represent row operations on G, meaning that the matrix G′ may have the columns of the identity matrix in G to different locations in G′.

Abstract translation: 改进的技术涉及为冗余磁盘阵列的每个数据条带分配不同的发生器矩阵，使得所有不同的发生器矩阵表示相同的代码。 例如，当ak×n生成矩阵G表示线性码C时，k为码长，n为码长，则对于任意的可逆k×k矩阵P，矩阵G'= PG也是表示C 当C是系统代码时，G由表示与表示奇偶校验数据的ak×（n-k）个奇偶校验矩阵连接的有效载荷数据的ak×k个单位矩阵组成。 某些矩阵P表示G上的行操作，这意味着矩阵G'可以具有G中的单位矩阵的列到G'中的不同位置。

公开(公告)号：US09304872B2

公开(公告)日：2016-04-05

申请号：US13821837

申请日：2011-09-09

Applicant: Andre Schmitt ,  Ute Schiffel ,  Christof Fetzer ,  Martin Suesskraut

Inventor： Andre Schmitt ,  Ute Schiffel ,  Christof Fetzer ,  Martin Suesskraut

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/08 ,  G06F11/28 ,  H03M13/47 ,  H03M13/49 ,  H03M13/51

CPC classification number: G06F11/1479 ,  G06F11/085 ,  G06F11/28 ,  H03M13/47 ,  H03M13/49 ,  H03M13/51

Abstract: In one embodiment, a method is provided for data processing in order to provide a value for determining whether an error has occurred in the execution of a program. The method may include: determining a numerical value on the basis of a plurality of reference numbers determined by a checking circuit outside the program; determining a signature of at least one instruction of the program by means of an arithmetic code; updating a cumulative value on the basis of the numerical value and the signature; and transferring the updated cumulative value to the checking circuit in order to determine whether an error has occurred in the execution of the program, on the basis of the plurality of reference numbers and the cumulative value.

Abstract translation: 在一个实施例中，提供了一种用于数据处理的方法，以便提供用于确定在执行程序中是否发生错误的值。 该方法可以包括：基于由程序外部的检查电路确定的多个参考号确定数值; 通过算术代码确定程序的至少一个指令的签名; 基于数值和签名更新累积值; 并且将更新的累积值转移到检查电路，以便基于多个参考号和累积值来确定在执行程序中是否发生错误。

公开(公告)号：US20160093354A1

公开(公告)日：2016-03-31

申请号：US14502287

申请日：2014-09-30

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G11C11/16 ,  G06F11/08

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract translation: 在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。 例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配 位单元格。

公开(公告)号：US09292376B2

公开(公告)日：2016-03-22

申请号：US13975112

申请日：2013-08-23

Applicant: VMware, Inc.

Inventor： Joanne Ren ,  Keith Farkas ,  Elisha Ziskind ,  Igor Tarashansky ,  Manoj Krishnan

IPC: G06F11/00 ,  G06F11/08 ,  G06F9/455 ,  G06F11/20 ,  G06F9/50

CPC classification number: G06F11/08 ,  G06F9/455 ,  G06F9/45558 ,  G06F9/5077 ,  G06F11/1484 ,  G06F11/20 ,  G06F11/2033 ,  G06F11/2069 ,  G06F11/301 ,  G06F2009/45591 ,  G06F2201/805 ,  G06F2201/815 ,  G06F2209/5014

Abstract: A system for proactive resource reservation for protecting virtual machines. The system includes a cluster of hosts, wherein the cluster of hosts includes a master host, a first slave host, and one or more other slave hosts, and wherein the first slave host executes one or more virtual machines thereon. The first slave host is configured to identify a failure that impacts an ability of the one or more virtual machines to provide service, and calculate a list of impacted virtual machines. The master host is configured to receive a request to reserve resources on another host in the cluster of hosts to enable the impacted one or more virtual machines to failover, calculate a resource capacity among the cluster of hosts, determine whether the calculated resource capacity is sufficient to reserve the resources, and send an indication as to whether the resources are reserved.

Abstract translation: 用于保护虚拟机的主动资源预留系统。 该系统包括一组主机，其中主机集群包括主主机，第一从机主机和一个或多个其他从机主机，并且其中第一从机主机在其上执行一个或多个虚拟机。 第一个从属主机被配置为识别影响一个或多个虚拟机提供服务的能力的故障，并计算受影响的虚拟机的列表。 主主机被配置为接收在主机群集中的另一个主机上预留资源的请求，以使受影响的一个或多个虚拟机故障转移，计算主机群集之间的资源容量，确定计算出的资源容量是否足够 保留资源，并发送资源是否保留。

公开(公告)号：US09280413B2

公开(公告)日：2016-03-08

申请号：US14105014

申请日：2013-12-12

Applicant: Talkatone, LLC

Inventor： Vadim Tsyganok

IPC: G06F11/00 ,  G06F11/08

CPC classification number: G06F11/076 ,  G06F11/0721 ,  G06F11/08 ,  H04L1/0009 ,  H04L1/08 ,  H04L1/203 ,  H04L43/0823

Abstract: Error events are tracked. The error events are classified based on a number of errors included in each event. A desired level of error event to be able to be corrected in order to maintain an acceptable rate of uncorrected errors is determined. A redundancy level is selected so that new error events corresponding to the desired level of error event or a lower level of error event are corrected.

Abstract translation: 跟踪错误事件。 错误事件根据每个事件中包含的错误数量进行分类。 确定为了维持可校正误差的可接受率，能够纠正所需的错误事件级别。 选择冗余级别，以便纠正对应于期望的错误事件级别或较低级别的错误事件的新的错误事件。

公开(公告)号：US09262260B2

公开(公告)日：2016-02-16

申请号：US13958062

申请日：2013-08-02

Applicant: FUJITSU LIMITED

Inventor： Yasumasa Oshiro

IPC: G06F11/00 ,  G06F11/08 ,  G06F11/34 ,  G06F11/20 ,  G06F11/30

CPC classification number: G06F11/08 ,  G06F11/0706 ,  G06F11/0766 ,  G06F11/2094 ,  G06F11/3006 ,  G06F11/3476 ,  G06F17/40 ,  G06F2201/86

Abstract: An information processing apparatus includes: a storage including storage areas individually allocated to processing operations, and is configured to store therein association information in which a content of a failure occurring in one processing operation of the processing operations and at least one storage area of the storage areas are associated with each other wherein history information indicating histories of the individual processing operations is stored in the individual storage areas in response to the execution of the processing operations; and a processor coupled to the storage and configured to duplicate, in a storage area different from the storage areas, history information stored in a storage area where a failure having occurred and a matching content of a failure are associated with each other in the association information when the failure has occurred in one processing operation of the processing operations.

Abstract translation: 一种信息处理装置，包括：存储部，其具有分别分配给处理动作的存储区域，并且被配置为在其中存储关联信息，所述关联信息中的处理操作的一个处理操作中发生的故障的内容和所述存储器的至少一个存储区域 区域相互关联，其中响应于处理操作的执行，指示各个处理操作的历史的历史信息被存储在各个存储区域中; 以及处理器，其耦合到所述存储器并且被配置为在存储区域中复制存储在存储区域中的历史信息，所述历史信息已经发生故障并且故障的匹配内容在所述关联信息中彼此相关联 当处理操作的一个处理操作中发生故障时。

公开(公告)号：US09262259B2

公开(公告)日：2016-02-16

申请号：US13741248

申请日：2013-01-14

Applicant: QUALCOMM Incorporated

Inventor： Asaf Ashkenazi

IPC: G06F21/78 ,  G06F11/08 ,  G06F21/71 ,  H04L9/00

CPC classification number: G06F11/08 ,  G06F21/71 ,  G06F21/78 ,  H04L9/004

Abstract: One-time programmable integrated circuit security is described. An example of a method of protecting memory assets in an integrated circuit includes sampling values of multiple OTP memory arrays and comparing the sampled value of each OTP memory array with the sampled value of each other OTP memory array and with an unprogrammed OTP memory array value. The method further includes determining if an integrated circuit performance fault has occurred based on the compared sampled values, booting the integrated circuit, and operating the integrated circuit with access to memory determined by the fault occurrence determination.

Abstract translation: 描述了一次性可编程集成电路安全性。 保护集成电路中的存储资产的方法的示例包括多个OTP存储器阵列的采样值，并将每个OTP存储器阵列的采样值与每个其它OTP存储器阵列的采样值以及未编程的OTP存储器阵列值进行比较。 该方法还包括基于所比较的采样值确定集成电路性能故障是否发生，启动集成电路，以及通过故障发生确定确定的对存储器的操作来操作集成电路。

公开(公告)号：US09195550B2

公开(公告)日：2015-11-24

申请号：US13020228

申请日：2011-02-03

Applicant: Dan Tsafrir ,  Robert W. Wisniewski

Inventor： Dan Tsafrir ,  Robert W. Wisniewski

IPC: G06F11/08 ,  G06F11/14 ,  G06F9/38 ,  G06F12/08 ,  G06F9/46 ,  G06F9/52

CPC classification number: G06F11/1489 ,  G06F9/3851 ,  G06F9/466 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0842 ,  G06F12/0846

Abstract: A method for checking program correctness may include executing a program on a main hardware thread in speculative execution mode on a hardware execution context on a chip having a plurality of hardware execution contexts. In this mode, the main hardware thread's state is not committed to main memory. Correctness checks by a plurality of helper threads are executed in parallel to the main hardware thread. Each helper thread runs on a separate hardware execution context on the chip in parallel with the main hardware thread. The correctness checks determine a safe point in the program up to which the operations executed by the main hardware thread are correct. Once the main hardware thread reaches the safe point, the mode of execution of the main hardware thread is switched to non-speculative. The runtime then causes the main thread to re-enter speculative mode of execution.

Abstract translation: 用于检查程序正确性的方法可以包括在具有多个硬件执行上下文的芯片上的硬件执行上下文上以推测执行模式在主硬件线程上执行程序。 在这种模式下，主硬件线程的状态不会被提供给主内存。 多个辅助线程的正确性检查与主硬件线程并行执行。 每个辅助线程与主要硬件线程并行运行在芯片上的单独硬件执行环境上。 正确性检查确定程序中的安全点，主要硬件线程执行的操作是正确的。 一旦主要硬件线程到达安全点，主硬件线程的执行模式切换为非投机模式。 然后运行时使主线程重新输入推测的执行模式。

公开(公告)号：US09195534B2

公开(公告)日：2015-11-24

申请号：US13772909

申请日：2013-02-21

Applicant: Siemens Aktiengesellschaft

Inventor： Jan Richter ,  Andreas Schenk ,  Karl-Hermann Witte

IPC: G06F11/07 ,  G06F11/00 ,  G06F11/08

CPC classification number: G06F11/0778 ,  G06F11/006 ,  G06F11/0763 ,  G06F11/085

Abstract: A method for storing and propagating error information in computer programs, in which a globally valid error variable is used for storing and propagating the error information, wherein for each recognized error a nonzero value for the error is added to the error variable as error information with a respective stipulated arithmetic sign, and wherein the value is formed from a discrepancy in the content of a coded variable from an expected value. This combination and integration of a separate global propagation variable with values derived from an error, particularly by virtue of detected discrepancies in the known error recognition and propagation paths using operations and operands in “coded processing”, achieves an increased propagation certainty.

Abstract translation: 一种在计算机程序中存储和传播错误信息的方法，其中使用全局有效的误差变量来存储和传播错误信息，其中对于每个识别的错误，将错误的非零值作为错误信息添加到错误信息中， 相应规定的算术符号，并且其中所述值由编码变量的内容与预期值的差异形成。 单独的全局传播变量与从错误导出的值的组合和集成，特别是通过使用“编码处理”中的操作和操作数的已知误差识别和传播路径中的检测到的差异实现了增加的传播确定性。

公开(公告)号：US09183077B2

公开(公告)日：2015-11-10

申请号：US14143532

申请日：2013-12-30

Applicant: FUJITSU LIMITED

Inventor： Katsuya Tsushita

IPC: G11C29/00 ,  G06F11/08 ,  G11C5/00 ,  G11C7/10

CPC classification number: G06F11/08 ,  G06F11/1048 ,  G11C5/005 ,  G11C7/1006

Abstract: A data storage apparatus includes: a memory configured to store data; an input delay circuit configured to input a set of data of a plurality of bits into the memory at different timings between the plurality of bits by adding different delays to the plurality of bits in the set of data or by adding different delays to bits in bit groups obtained by grouping the plurality of bits in units of a consecutive bits; and an output delay circuit configured to obtain an original set of data, which is the set of data before the input delay circuit adds the different delays, by adding, to the plurality of bits in the set of data output from the memory, delays having a pattern opposite that of the delays added by the input delay circuit.

Abstract translation: 数据存储装置包括：存储器，被配置为存储数据; 输入延迟电路，被配置为通过向数据集合中的多个比特添加不同的延迟，或者通过向比特中添加不同的延迟，将多个比特的一组数据输入到多个比特之间的不同定时 通过以连续比特为单位对多个比特进行分组而获得的组; 以及输出延迟电路，被配置为通过将从存储器输出的数据组中的多个比特相加来获得作为输入延迟电路在不同延迟之前的数据集的原始数据集合， 与由输入延迟电路相加的延迟相反的模式。