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公开(公告)号：US20240170411A1
公开(公告)日：2024-05-23
申请号：US18057135
申请日：2022-11-18
Inventor： Xu CHANG , Rajesh KATKAR
IPC: H01L23/544 , H01L21/683 , H01L21/78 , H01L23/00
CPC classification number: H01L23/544 , H01L21/6835 , H01L21/78 , H01L24/08 , H01L24/80 , H01L2223/5446 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896
Abstract: This disclosure relates to systems and methods for reinforced semiconductor structures. In some embodiments, an assembly can include a substrate having a top surface and a bottom surface and one or more layers formed on the top surface of the substrate. The one or more layers and the substrate can comprise a plurality of devices to be singulated into dies and a scribe region separating the devices, at least one layer of the one more layers comprising a first dielectric material. The one or more layers and substrate can also include a trench at least partially overlapping the scribe region and at least partially filled with a second dielectric material, wherein the second dielectric material has a higher dielectric constant than a dielectric constant of the first dielectric material, or otherwise more resistant to chipping or cracking than the first dielectric material.
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公开(公告)号：US20240136196A1
公开(公告)日：2024-04-25
申请号：US18475977
申请日：2023-09-26
Inventor： Jeremy Alfred Theil
IPC: H01L21/3105 , H01L21/02 , H01L21/311 , H01L23/00
CPC classification number: H01L21/31053 , H01L21/0217 , H01L21/31111 , H01L24/83 , H01L2224/83031 , H01L2224/83896
Abstract: Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.
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73.发明授权公开(公告)号：US11967575B2
公开(公告)日：2024-04-23
申请号：US17681019
申请日：2022-02-25
Inventor： Guilian Gao , Javier A. DeLaCruz , Shaowu Huang , Liang Wang , Gaius Gillman Fountain, Jr. , Rajesh Katkar , Cyprian Emeka Uzoh
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L24/05 , H01L24/06 , H01L24/74 , H01L24/80 , H01L24/89 , H01L2224/05557 , H01L2224/06131 , H01L2224/06177 , H01L2224/08147 , H01L2224/80007 , H01L2224/80011 , H01L2224/80031 , H01L2224/80047 , H01L2224/8013 , H01L2224/80895 , H01L2224/80896 , H01L2924/3512
Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
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公开(公告)号：US20240128186A1
公开(公告)日：2024-04-18
申请号：US18394558
申请日：2023-12-22
Inventor： Belgacem Haba , Javier A. DeLaCruz
IPC: H01L23/522 , H01L23/00 , H01L23/528 , H01L23/538 , H01L25/16
CPC classification number: H01L23/5223 , H01L23/5226 , H01L23/5286 , H01L23/5383 , H01L23/5389 , H01L24/17 , H01L25/16 , H01L28/60 , H01L2924/1205
Abstract: In various embodiments, a passive electronic component is disclosed. The passive electronic component can have a first surface and a second surface opposite the first surface. The passive electronic component can include a nonconductive material and a capacitor embedded within the nonconductive material. The capacitor can have a first electrode, a second electrode, and a dielectric material disposed between the first and second electrodes. The first electrode can comprise a first conductive layer and a plurality of conductive fibers extending from and electrically connected to the first conductive layer. A first conductive via can extend through the passive electronic component from the first surface to the second surface, with the first conductive via electrically connected to the first electrode.
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75.发明公开公开(公告)号：US20240118492A1
公开(公告)日：2024-04-11
申请号：US18508556
申请日：2023-11-14
Inventor： Shaowu HUANG , Javier A. DELACRUZ , Liang WANG , Guilian GAO
IPC: G02B6/13
CPC classification number: G02B6/13 , G02B2006/12097
Abstract: Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.
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Patent Agency Ranking
公开(公告)号：US20240096823A1
公开(公告)日：2024-03-21
申请号：US18520337
申请日：2023-11-27
Inventor： Javier A. DeLaCruz , Belgacem Haba , Rajesh Katkar
IPC: H01L23/00 , H01L21/66 , H01L23/528
CPC classification number: H01L23/573 , H01L22/34 , H01L23/528 , H01L23/562 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/49 , H01L2224/08237 , H01L2224/29082 , H01L2224/29187 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48225 , H01L2224/49171 , H01L2224/73215
Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.
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公开(公告)号：US20240096683A1
公开(公告)日：2024-03-21
申请号：US18368971
申请日：2023-09-15
Inventor： Cyprian Emeka Uzoh , Aaron Todd Francis , Gabriel Guevara , Thomas Workman , Dominik Suwito
IPC: H01L21/683
CPC classification number: H01L21/6835 , H01L2221/68309 , H01L2221/68313 , H01L2221/68354
Abstract: Embodiments herein are generally directed to die cleaning frames for processing and handling singulated devices and methods related thereto. The die cleaning frames may be used advantageously to minimize contact with device surfaces during post-singulation processing and to facilitate a pick and place bonding process without touching the active side of the cleaned device. Thus, the die cleaning frames and methods described herein eliminate the need for undesirable contact with clean and prepared active sides of the devices during a direct placement die-to-wafer bonding process. In one embodiment, a carrier configured to support a singulated device in a die pocket region may include a carrier plate and a frame that surrounds the carrier plate and is integrally formed therewith. The carrier plate may include a first surface and an opposite second surface, and one or more sidewalls that define an opening disposed through and extending between the first and second surfaces. Each of the sidewalls may include one or more protuberances that collectively determine a rectangular boundary of the die pocket region. Some of the protuberances may include a die supporting surface that extends beneath the die pocket region.
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公开(公告)号：US20230420399A1
公开(公告)日：2023-12-28
申请号：US18462691
申请日：2023-09-07
Inventor： Belgacem Haba , Rajesh Katkar , Ilyas Mohammed , Javier A. DeLaCruz
CPC classification number: H01L24/08 , H01L24/80 , H01L24/94 , H01L21/78 , H01L2224/80896 , H01L2224/08146 , H01L2224/80006 , H01L2224/80895
Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
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公开(公告)号：US20230420313A1
公开(公告)日：2023-12-28
申请号：US18463080
申请日：2023-09-07
Inventor： Rajesh Katkar , Liang Wang , Cyprian Emeka Uzoh , Shaowu Huang , Guilian Gao , Ilyas Mohammed
CPC classification number: H01L23/10 , B81C1/00333 , B81B7/0074 , B81B7/0032 , B81C1/00261 , H01L23/04 , H01L23/053 , H01L23/02 , B81C1/00269 , B81C2203/038
Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
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公开(公告)号：US11855064B2
公开(公告)日：2023-12-26
申请号：US17344100
申请日：2021-06-10
IPC: H01L25/00 , H01L25/065 , H01L23/00 , H01L21/78 , H01L21/683 , H01L21/18
CPC classification number: H01L25/50 , H01L21/187 , H01L21/6836 , H01L21/78 , H01L24/27 , H01L24/30 , H01L24/83 , H01L25/0657 , H01L2224/83011 , H01L2224/83013
Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.
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