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    Method for manufacturing MEMS torsional electrostatic actuator
    71.
    发明授权
    Method for manufacturing MEMS torsional electrostatic actuator 有权

    公开(公告)号：US09834437B2

    公开(公告)日：2017-12-05

    申请号：US15327230

    申请日：2015-07-31

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

    Inventor： Errong Jing

    IPC: B81C1/00 ,  B81B3/00

    CPC classification number: B81C1/00182 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2203/058 ,  B81C1/00603 ,  B81C2201/0109 ,  B81C2201/0111

    Abstract: A method for manufacturing an MEMS torsional electrostatic actuator comprises: providing a substrate, wherein the substrate comprises a first silicon layer, a buried oxide layer and a second silicon layer that are laminated sequentially; patterning the first silicon layer and exposing the buried oxide layer to form a rectangular upper electrode plate separated from a peripheral region, wherein the upper electrode plate and the peripheral region are connected by only using a cantilever beam, and forming, on the peripheral region, a recessed portion exposing the buried oxide layer; patterning the second silicon layer and exposing the buried oxide layer to form a back cavity, wherein the back cavity is located in a region of the second silicon layer corresponding to the upper electrode plate, covers 40% to 60% of the area of the region corresponding to the upper electrode plate, and is close to one end of the cantilever beam; exposing the second silicon layer, and suspending the upper electrode plate and the cantilever beam; and respectively forming an upper contact electrode and a lower contact electrode on the second silicon layer.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
    73.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开

    公开(公告)号：US20170222012A1

    公开(公告)日：2017-08-03

    申请号：US15328623

    申请日：2015-09-02

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

    Inventor： Long HAO ,  Yan JIN ,  Wei LI

    IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66

    CPC classification number: H01L29/4916 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/04 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66568

    Abstract: A manufacturing method for a semiconductor device is provided. The method comprises: providing a semiconductor substrate (200); sequentially forming an oxide layer (201) and a silicon nitride layer (202) on the semiconductor substrate (200); annealing the silicon nitride layer (202), and then etching an active region (401) by using the silicon nitride layer (202) as a mask, so as to form in the semiconductor substrate (200) a trench (203) for filling an isolation material, wherein the active region (401) comprises a gate region (403) and a source region (404) and a drain region (405) that are respectively located on two sides of the gate region (403), and the gate region (403) comprises a body part connected to the source region (404) and the drain region (405) and a protruding part (406) that protrudes and extends from the body part to the trench; etching-back the silicon nitride layer (202) and forming a lining oxide layer (201) on the sidewall and the bottom of the trench; depositing an isolation material layer (205) to fill the trench; grinding the isolation material layer (205) until the top of the silicon nitride layer (202) is exposed; and etching to remove the silicon nitride layer (202).

    BROWN OUT DETECTOR HAVING SEQUENTIAL CONTROL FUNCTION
    74.
    发明申请
    BROWN OUT DETECTOR HAVING SEQUENTIAL CONTROL FUNCTION 审中-公开

    公开(公告)号：US20170205470A1

    公开(公告)日：2017-07-20

    申请号：US15327956

    申请日：2015-06-30

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

    Inventor： Youhui LI ,  Xiaoli XU

    IPC: G01R31/40 ,  G01R19/165 ,  G01R15/04

    CPC classification number: G01R31/40 ,  G01R15/04 ,  G01R19/165 ,  G01R19/16552 ,  G06F1/28

    Abstract: A brown-out detection circuit having a time sequence control function comprises: a voltage divider (110), a reference voltage source (120), a comparator (130) and a time sequence control module (140); wherein one terminal of the voltage divider (110) is connected to an external power supply, the other terminal of the voltage divider (110) is connected to a positive input of the comparator (130), the reference voltage source (120) is connected to an inverted input of the comparator (130), the time sequence control module (140) is connected to an output of the comparator (130), an output of the time sequence control module (140) serves as an output of the brown-out detection circuit; when a duration of a power supply voltage lower than a reference voltage is not shorter than a preset time, the time sequence control module (140) controls the output of the brown-out detection circuit to be inverted from a high level to a low level.

    METHOD FOR MANUFACTURING MEMS TORSIONAL ELECTROSTATIC ACTUATOR
    75.
    发明申请
    METHOD FOR MANUFACTURING MEMS TORSIONAL ELECTROSTATIC ACTUATOR 有权

    公开(公告)号：US20170174508A1

    公开(公告)日：2017-06-22

    申请号：US15327230

    申请日：2015-07-31

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

    Inventor： Errong JING

    IPC: B81C1/00 ,  B81B3/00

    CPC classification number: B81C1/00182 ,  B81B3/0021 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2203/058 ,  B81C1/00603 ,  B81C2201/0109 ,  B81C2201/0111

    Abstract: A method for manufacturing an MEMS torsional electrostatic actuator comprises: providing a substrate, wherein the substrate comprises a first silicon layer, a buried oxide layer and a second silicon layer that are laminated sequentially; patterning the first silicon layer and exposing the buried oxide layer to form a rectangular upper electrode plate separated from a peripheral region, wherein the upper electrode plate and the peripheral region are connected by only using a cantilever beam, and forming, on the peripheral region, a recessed portion exposing the buried oxide layer; patterning the second silicon layer and exposing the buried oxide layer to form a back cavity, wherein the back cavity is located in a region of the second silicon layer corresponding to the upper electrode plate, covers 40% to 60% of the area of the region corresponding to the upper electrode plate, and is close to one end of the cantilever beam; exposing the second silicon layer, and suspending the upper electrode plate and the cantilever beam; and respectively forming an upper contact electrode and a lower contact electrode on the second silicon layer.

    POSITIONING METHOD IN MICROPROCESSING PROCESS OF BULK SILICON
    77.
    发明申请
    POSITIONING METHOD IN MICROPROCESSING PROCESS OF BULK SILICON 有权

    公开(公告)号：US20170113930A1

    公开(公告)日：2017-04-27

    申请号：US15315640

    申请日：2015-08-19

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

    Inventor： Errong JING

    IPC: B81C3/00

    CPC classification number: B81C3/004 ,  B81C1/00 ,  B81C1/00603 ,  B81C3/00 ,  B81C2203/051 ,  G03F9/00 ,  H01L21/68

    Abstract: A positioning method in a microprocessing process of bulk silicon comprises the steps of: fabricating, on a first surface of a first substrate (10), a first pattern (100), a stepper photo-etching machine alignment mark (200) for positioning the first pattern, and a double-sided photo-etching machine first alignment mark (300) for positioning the stepper photo-etching machine alignment mark; fabricating, on a second surface, opposite to the first surface, of the first substrate, a double-sided photo-etching machine second alignment mark (400) corresponding to the double-sided photo-etching machine first alignment mark; bonding a second substrate (20) on the first surface of the first substrate; performing thinning on a first surface of the second substrate; fabricating, on the first surface of the second substrate, a double-sided photo-etching machine third alignment mark (500) corresponding to the double-sided photo-etching machine second alignment mark; and finding, on the first surface of the second substrate by using the double-sided photo-etching machine third alignment mark, a corresponding position of the stepper photo-etching machine alignment mark.

    MEMS MICROPHONE
    79.
    发明申请
    MEMS MICROPHONE 有权
    MEMS麦克风

    公开(公告)号：US20170070824A1

    公开(公告)日：2017-03-09

    申请号：US15119878

    申请日：2015-06-25

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

    Inventor： Yonggang HU

    IPC: H04R19/04 ,  B81B3/00 ,  H04R7/16

    CPC classification number: H04R19/04 ,  B81B3/0037 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  G01L9/0045 ,  G01L9/0073 ,  H04R7/12 ,  H04R7/14 ,  H04R7/16 ,  H04R19/005 ,  H04R2201/003

    Abstract: A MEMS microphone includes a substrate (100), a supporting part (200), an upper polar plate (300) and a lower polar plate (400). The substrate (100) is provided with an opening (120) penetrating the middle thereof; the lower polar plate (400) straddles the opening (120); the supporting part (200) is fixed on the lower polar plate (400); the upper polar plate (300) is affixed to the supporting part (200); an accommodating cavity (500) is formed among the supporting part (200), the upper polar plate (300) and the lower polar plate (400); a recess (600) opposite to the accommodating cavity (500) is arranged in an intermediate region of at least one of the upper polar plate (300) and the lower polar plate (400), and insulation is achieved between the upper polar plate (300) and a lower polar plate (400).

    Abstract translation: MEMS麦克风包括基板（100），支撑部件（200），上极板（300）和下极板（400）。 基板（100）设有贯穿其中间的开口（120） 所述下极板（400）跨越所述开口（120）; 支撑部分（200）固定在下极板（400）上; 上极板300固定在支撑部200上。 在支撑部件（200），上极板（300）和下极板（400）之间形成容纳空腔（500）; 在所述上极板（300）和所述下极板（400）中的至少一个的中间区域中布置与所述容纳腔（500）相对的凹部（600），并且在所述上极板 300）和下极板（400）。

    LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
    80.
    发明申请
    LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 有权
    侧向扩散金属氧化物半导体器件及其制造方法

    公开(公告)号：US20170054018A1

    公开(公告)日：2017-02-23

    申请号：US15119868

    申请日：2015-05-04

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

    Inventor： Guangsheng ZHANG ,  Sen ZHANG

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

    Abstract: A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure. The source region (41) is located in the well region (34); the drain region (34) is located in the super junction structure; the gate region comprises a gate oxide layer and a gate electrode on the gate oxide layer; and the super junction structure comprises a plurality of N-columns and P-columns, wherein the N-columns and the P-columns are alternately arranged in a direction which is horizontal and is perpendicular to the direction of a connecting line between the source region and the drain region, each N-column comprises a top-layer N-region (23) and a bottom-layer N-region which are butted vertically, and each P-column comprises a top-layer P-region (24) and a bottom-layer P-region which are butted vertically.

    Abstract translation: 横向扩散的金属氧化物半导体器件包括：衬底（10）; 衬底中的掩埋层区域（32）; 掩埋层区域（32）上的阱区（34）; 井区域上的栅极区域; 源区域（41）和漏极区域（43），位于栅极区域的两侧; 和超结结构。 源极区域（41）位于阱区域（34）中。 漏区（34）位于超结结构中; 栅极区域包括栅极氧化物层和栅极氧化物层上的栅电极; 并且超结结构包括多个N列和P列，其中N列和P列在水平方向上交替布置，并且垂直于源极区域之间的连接线的方向 和漏极区域，每个N列包括垂直对接的顶层N区（23）和底层N区，每个P列包括顶层P区（24）和 垂直对接的底层P区。

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