公开(公告)号：US09735243B2

公开(公告)日：2017-08-15

申请号：US14082491

申请日：2013-11-18

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L27/115 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

公开(公告)号：US20170076961A1

公开(公告)日：2017-03-16

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/56 ,  H01L27/02 ,  H01L23/498 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US09455205B2

公开(公告)日：2016-09-27

申请号：US14055982

申请日：2013-10-17

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler ,  Peter Nelle ,  Ludger Borucki ,  Markus Winkler ,  Erwin Vogl

IPC: G01R31/26 ,  H01L21/66

CPC classification number: H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential.

Abstract translation: 根据各种实施例的用于处理半导体器件的方法可以包括：提供具有第一焊盘和与第一焊盘电连接的第二焊盘的半导体器件; 对所述第一焊盘和所述第二焊盘中的至少一个施加至少一个电测试电位; 以及在施加所述至少一个电测试电位之后将所述第一焊盘和所述第二焊盘彼此电连接。

公开(公告)号：US20160233330A1

公开(公告)日：2016-08-11

申请号：US15132709

申请日：2016-04-19

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Dietrich Bonart ,  Ludger Borucki

IPC: H01L29/78 ,  H02J7/24 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7802 ,  H01L23/051 ,  H01L23/24 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/7391 ,  H01L29/861 ,  H01L2924/0002 ,  H02J7/14 ,  H02J7/242 ,  H01L2924/00

Abstract: A gated diode in a press-fit housing includes a base configured to be press-fit into an opening of a diode carrier plate and including a pedestal portion with a first flat surface, and a head wire including a head portion with a second flat surface and a wire portion. The base and the head wire form parts of the press-fit housing. The gated diode in the press-fit housing further includes a semiconductor die, a first solder layer engaging and electrically connecting the semiconductor die with the first flat surface of the base, and a second solder layer engaging and electrically connecting the semiconductor die with the second flat surface of the head wire.

Abstract translation: 压配合壳体中的门控二极管包括：基座，其被配置成压配合到二极管载体板的开口中并且包括具有第一平坦表面的基座部分，以及头部导线，其包括具有第二平坦表面的头部部分 和导线部分。 基座和头部线形成压配合壳体的一部分。 压配合壳体中的门控二极管还包括半导体管芯，将半导体管芯与基座的第一平坦表面接合并电连接的第一焊料层，以及将半导体管芯与第二焊盘接合并电连接的第二焊料层 平头表面的头线。

公开(公告)号：US09397092B2

公开(公告)日：2016-07-19

申请号：US14813738

申请日：2015-07-30

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel ,  Till Schloesser

IPC: H01L27/08 ,  H01L49/02 ,  H01L21/768 ,  H01L29/40 ,  H01L27/06 ,  H01L21/00

CPC classification number: H01L27/0805 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/407

Abstract: A semiconductor device in a semiconductor substrate includes a trench in a first main surface of the semiconductor substrate. The trench includes a first trench portion extending in a first direction and a second trench portion extending in the first direction. The first trench portion is connected with the second trench portion in a lateral direction. The first trench portion and the second trench portion are arranged one after the other along the first direction. The semiconductor device further includes a trench conductive structure having a conductive material disposed in the first trench portion, and a trench capacitor structure having a capacitor dielectric and a first capacitor electrode disposed in the second trench portion. The first capacitor electrode includes a layer lining a sidewall of the second trench portion.

Abstract translation: 半导体衬底中的半导体器件包括在半导体衬底的第一主表面中的沟槽。 沟槽包括沿第一方向延伸的第一沟槽部分和沿第一方向延伸的第二沟槽部分。 第一沟槽部分沿横向方向与第二沟槽部分连接。 第一沟槽部分和第二沟槽部分沿着第一方向一个接一个布置。 半导体器件还包括具有设置在第一沟槽部分中的导电材料的沟槽导电结构，以及具有电容器电介质的沟槽电容器结构和设置在第二沟槽部分中的第一电容器电极。 第一电容器电极包括衬在第二沟槽部分的侧壁上的层。

公开(公告)号：US09391192B2

公开(公告)日：2016-07-12

申请号：US14525398

申请日：2014-10-28

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Karl-Heinz Bach ,  Andrew Christopher Graeme Wood

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/0634 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815

Abstract: What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa.

Abstract translation: 提供的场效应部件包括半导体本体，该半导体本体从边缘区域延伸到从顶侧到侧面的后侧，并且包括半导体台面，该半导体台面垂直于后侧 和/或顶侧。 所述半导体本体在垂直截面中还包括漂移区域，所述漂移区域至少在所述边缘区域中至少延伸至所述顶侧并且部分地布置在所述半导体台面中，所述体区域至少部分地布置在 半导体台面并且与漂移区域形成pn结。 pn结在半导体台面的两个侧壁之间延伸。

公开(公告)号：US20160181417A1

公开(公告)日：2016-06-23

申请号：US14976604

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Christian Kampen ,  Markus Zundel

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/407 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/7813

Abstract: Disclosed is a transistor device. The transistor device includes a plurality of field structures which define a plurality of semiconductor mesa regions in a semiconductor body, and each of which comprises a field electrode and a field electrode dielectric; a plurality of gate structures in each semiconductor mesa region, wherein each gate structure comprises a gate electrode and a gate dielectric, and is arranged in a trench of the semiconductor mesa region; a plurality of body regions, a plurality of source regions, and a drift region. Each body region adjoins the gate dielectric of at least one of the plurality of gate structures, and is located between one of the plurality of source regions and the drift region.

Abstract translation: 公开了一种晶体管器件。 晶体管器件包括在半导体本体中限定多个半导体台面区域的多个场结构，并且每个场结构包括场电极和场电极电介质; 每个半导体台面区域中的多个栅极结构，其中每个栅极结构包括栅电极和栅极电介质，并且布置在半导体台面区域的沟槽中; 多个体区域，多个源区域和漂移区域。 每个体区域与多个栅极结构中的至少一个栅极结构的栅极电介质相邻，并且位于多个源极区域中的一个和漂移区域之间。

公开(公告)号：US20160141410A1

公开(公告)日：2016-05-19

申请号：US15004467

申请日：2016-01-22

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861

Abstract: One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.5 times the mutual distance between the trenches, and a doping concentration of the drift zone in a section between the trenches and the second semiconductor zone differs by at most 35% from a minimum doping concentration in a section between the trenches.

公开(公告)号：US09343565B2

公开(公告)日：2016-05-17

申请号：US14862236

申请日：2015-09-23

Applicant: Infineon Technologies AG

Inventor： Peter Nelle ,  Markus Zundel

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7808 ,  H01L27/0629 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7813 ,  H01L29/8613

Abstract: One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of transistor cells in a semiconductor body. A width w3 of a transistor mesa region of each of the plurality of transistor cells and a width w1 of a first trench of each of the plurality of transistor cells satisfy the following relationship: w3

Abstract translation: 半导体器件的一个实施例包括致密沟槽晶体管单元阵列。 密集沟槽晶体管单元阵列包括半导体本体中的多个晶体管单元。 多个晶体管单元的晶体管台面区域的宽度w3和多个晶体管单元中的每一个的第一沟槽的宽度w1满足以下关系：w3 <1.5×w1。 半导体器件还包括半导体二极管。 至少一个半导体二极管布置在多个晶体管单元的第一和第二部分之间，并且包括邻接第二沟槽的相对壁的二极管台面区域。 第一沟槽的深度d1和第二沟槽的深度d2相差至少20％。

公开(公告)号：US09257512B2

公开(公告)日：2016-02-09

申请号：US14514491

申请日：2014-10-15

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Franz Hirler

IPC: H01L29/40 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861

Abstract: One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.5 times the mutual distance between the trenches, and a doping concentration of the drift zone in a section between the trenches and the second semiconductor zone differs by at most 35% from a minimum doping concentration in a section between the trenches.