公开(公告)号：US11509069B2

公开(公告)日：2022-11-22

申请号：US16901243

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Adel A. Elsherbini

IPC: H01Q21/00 ,  H01Q21/22 ,  H01L23/00 ,  H01Q21/06 ,  H01Q23/00 ,  G06K19/077

Abstract: Embodiments described herein generally relate to phased array antenna systems or packages and techniques of making and using the systems and packages. A phased array antenna package may include a distributed phased array antenna comprising (1) a plurality of antenna sub-arrays, which may each include a plurality of antennas, (2) a plurality of Radio Frequency Dies (RFDs), each of the RFDs located proximate and electrically coupled by a trace of a plurality of traces to a corresponding antenna sub-array of the plurality of antenna sub-arrays, and (3) wherein each trace of the plurality of traces configured to electrically couple an antenna of the plurality of antennas to the RFD located proximate the antenna, wherein each trace of the plurality of traces is configured to transmit millimeter wave (mm-wave) radio signals, and wherein the plurality of traces are each of a substantially uniform length.

公开(公告)号：US11469206B2

公开(公告)日：2022-10-11

申请号：US16008879

申请日：2018-06-14

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Shawna M. Lift

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

公开(公告)号：US20220319996A1

公开(公告)日：2022-10-06

申请号：US17842600

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

公开(公告)号：US11462463B2

公开(公告)日：2022-10-04

申请号：US16145059

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01F27/24 ,  H01L49/02 ,  G05F1/46 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

公开(公告)号：US11437348B2

公开(公告)日：2022-09-06

申请号：US17128558

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Amr Elshazly ,  Arun Chandrasekhar ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US20220223578A1

公开(公告)日：2022-07-14

申请号：US17712339

申请日：2022-04-04

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Arun Chandrasekhar

IPC: H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US20220189839A1

公开(公告)日：2022-06-16

申请号：US17122167

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Aleksandar Aleksov

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include an interposer; a first microelectronic component having a first surface coupled to the interposer by a first direct bonding region and an opposing second surface; a second microelectronic component having a first surface coupled to the interposer by a second direct bonding region and an opposing second surface; a liner material on the surface of the interposer and around the first and second microelectronic components; an inorganic fill material on the liner material and between the first and second microelectronic components; and a third microelectronic component coupled to the second surfaces of the first and second microelectronic components. In some embodiments, the liner material, the inorganic fill material, and a material of the third microelectronic component may include a thermally conductive material.

公开(公告)号：US20220102270A1

公开(公告)日：2022-03-31

申请号：US17548728

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/552 ,  H01L23/00 ,  H01L27/02

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.

公开(公告)号：US20210410343A1

公开(公告)日：2021-12-30

申请号：US17468510

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Feras Eid

IPC: H05K9/00 ,  H01L23/60 ,  H01L21/48 ,  C08G61/12 ,  C08G73/06 ,  C08G85/00

Abstract: Embodiments may relate to a microelectronic package comprising: a die and a package substrate coupled to the die with a first interconnect on a first face. The package substrate comprises: a second interconnect and a third interconnect on a second face opposite to the first face; a conductive signal path between the first interconnect and the second interconnect; a conductive ground path between the second interconnect and the third interconnect; and an electrostatic discharge (ESD) protection material coupled to the conductive ground path. The ESD protection material comprises a first electrically-conductive carbon allotrope having a first functional group, a second electrically-conductive carbon allotrope having a second functional group, and an electrically-conductive polymer chemically bonded to the first functional group and the second functional group permitting an electrical signal to pass between the first and second electrically-conductive carbon allotropes.

公开(公告)号：US20210193595A1

公开(公告)日：2021-06-24

申请号：US16721327

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L23/60 ,  H05K1/18 ,  H01L27/02 ,  H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.