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公开(公告)号：US09633405B2
公开(公告)日：2017-04-25
申请号：US13936000
申请日：2013-07-05
Applicant: Imagination Technologies Limited
Inventor： Steven J. Fishwick , John W. Howson
CPC classification number: G06T1/20 , G06T1/00 , G06T15/005
Abstract: A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.
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72.发明申请Graphics Processing Method and System for Processing Sub-Primitives Using Sub-Primitive Indications in a Control Stream 审中-公开用于在控制流中使用子原始指示处理子原语的图形处理方法和系统公开(公告)号：US20170069132A1
公开(公告)日：2017-03-09
申请号：US15259299
申请日：2016-09-08
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Xile Yang , Andrea Sansottera , Lorenzo Belli , Jonathan Redshaw
CPC classification number: G06T17/20 , G06T1/20 , G06T11/40 , G06T15/005 , G06T15/40 , G06T17/205
Abstract: When untransformed display lists are used in a tile-based graphics processing system, the processing involved in deriving sub-primitives may need to be performed in both the geometry processing phase and the rasterisation phase. To reduce the duplication of this processing, the control stream data for a tile includes sub-primitive indications to indicate which sub-primitives are to be used for rendering a tile. This allows the sub-primitives to be determined efficiently in the rasterisation phase based on this information determined in the geometry processing phase. Furthermore, a hierarchical cache system may be used to store a hierarchy of graphics data items used for deriving sub-primitives. If graphics data items for deriving a sub-primitive are stored in the cache, the retrieval of these graphics data items from the cache in the rasterisation phase can reduce the amount of processing performed to derive the sub-primitives.
Abstract translation: 当在基于瓦片的图形处理系统中使用未转换的显示列表时，可能需要在几何处理阶段和光栅化阶段中执行导出子图元所涉及的处理。 为了减少该处理的重复，瓦片的控制流数据包括用于指示要用于渲染瓦片的哪些子图元的子原始指示。 这允许基于在几何处理阶段中确定的信息在光栅化阶段中有效地确定子图元。 此外，分级缓存系统可以用于存储用于导出子原语的图形数据项的层次。 如果用于导出子原语的图形数据项被存储在高速缓存中，则在光栅化阶段中从高速缓存中检索这些图形数据项可以减少为了导出子图元而执行的处理量。
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公开(公告)号：US09105131B2
公开(公告)日：2015-08-11
申请号：US13959414
申请日：2013-08-05
Applicant: Imagination Technologies Limited
Inventor： John W. Howson
Abstract: A method and an apparatus are provided for combining multiple independent tile-based graphic cores. A block of geometry, containing a plurality of triangles, is split into sub-portions and sent to different geometry processing units. Each geometry processing unit generates a separate tiled geometry list that contains interleave markers that indicate an end to a sub-portion of a block of geometry overlapping a particular tile, processed by that geometry processing unit, and an end marker that identifies an end to all geometry processed for a particular tile by that geometry processing unit. The interleave markers are used to control an order of presentation of geometry to a hidden surface removal unit for a particular tile, and the end markers are used to control when the tile reference lists, for a particular tile, have been completely traversed.
Abstract translation: 提供了一种用于组合多个独立的基于瓦片的图形核心的方法和装置。 包含多个三角形的几何体块被分割成子部分并发送到不同的几何处理单元。 每个几何处理单元产生单独的平铺几何列表，其包含交错标记，其指示与由该几何处理单元处理的特定瓦片重叠的几何体块的子部分的结束以及标识所有的结束的结束标记 由几何处理单元为特定瓦片处理的几何图形。 交错标记用于控制几何的呈现顺序到用于特定瓦片的隐藏表面去除单元，并且结束标记用于控制对于特定瓦片的瓦片参考列表何时已被完全穿过。
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公开(公告)号：US20250166286A1
公开(公告)日：2025-05-22
申请号：US19028931
申请日：2025-01-17
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Luke T. Peterson
Abstract: Ray tracing units, processing modules and methods are described for generating one or more reduced acceleration structures to be used for intersection testing in a ray tracing system for processing a 3D scene. Nodes of the reduced acceleration structure(s) are determined, wherein a reduced acceleration structure represents a subset of the 3D scene. The reduced acceleration structure(s) are stored for use in intersection testing. Since the reduced acceleration structures represent a subset of the scene (rather than the whole scene) the memory usage for storing the acceleration structure is reduced, and the latency in the traversal of the acceleration structure is reduced.
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公开(公告)号：US20250157139A1
公开(公告)日：2025-05-15
申请号：US19020711
申请日：2025-01-14
Applicant: Imagination Technologies Limited
Inventor： John W. Howson
Abstract: 3-D rendering systems include a rasterization section that can fetch untransformed geometry, transform geometry and cache data for transformed geometry in a memory. As an example, the rasterization section can transform the geometry into screen space. The geometry can include one or more of static geometry and dynamic geometry. The rasterization section can query the cache for presence of data pertaining to a specific element or elements of geometry, and use that data from the cache, if present, and otherwise perform the transformation again, for actions such as hidden surface removal. The rasterization section can receive, from a geometry processing section, tiled geometry lists and perform the hidden surface removal for pixels within respective tiles to which those lists pertain.
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Patent Agency Ranking
公开(公告)号：US20250069317A1
公开(公告)日：2025-02-27
申请号：US18941958
申请日：2024-11-08
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Aroun Demeure , Steven Fishwick
Abstract: Methods of rendering a scene in a graphics system identify a draw call within a current render and analyse the last shader in the series of shaders used by the draw call to identify any buffers that are sampled by the last shader and that are to be written by a previous render that has not yet been sent for execution on the GPU. If any such buffers are identified, further analysis is performed to determine whether the last shader samples from the identified buffers using screen space coordinates that correspond to a current fragment location and if this determination is positive, the draw call is added to data relating to the previous render and the last shader is recompiled to replace an instruction that reads data from an identified buffer with an instruction that reads data from an on-chip register.
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公开(公告)号：US12217358B2
公开(公告)日：2025-02-04
申请号：US17888220
申请日：2022-08-15
Applicant: Imagination Technologies Limited
Inventor： John W. Howson
Abstract: 3-D rendering systems include a rasterization section that can fetch untransformed geometry, transform geometry and cache data for transformed geometry in a memory. As an example, the rasterization section can transform the geometry into screen space. The geometry can include one or more of static geometry and dynamic geometry. The rasterization section can query the cache for presence of data pertaining to a specific element or elements of geometry, and use that data from the cache, if present, and otherwise perform the transformation again, for actions such as hidden surface removal. The rasterization section can receive, from a geometry processing section, tiled geometry lists and perform the hidden surface removal for pixels within respective tiles to which those lists pertain.
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公开(公告)号：US12148084B2
公开(公告)日：2024-11-19
申请号：US18222968
申请日：2023-07-17
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Richard Broadhurst , Steven Fishwick
Abstract: A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.
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公开(公告)号：US12141909B2
公开(公告)日：2024-11-12
申请号：US18208676
申请日：2023-06-12
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Aroun Demeure , Steven Fishwick
Abstract: Methods of rendering a scene in a graphics system identify a draw call within a current render and analyse the last shader in the series of shaders used by the draw call to identify any buffers that are sampled by the last shader and that are to be written by a previous render that has not yet been sent for execution on the GPU. If any such buffers are identified, further analysis is performed to determine whether the last shader samples from the identified buffers using screen space coordinates that correspond to a current fragment location and if this determination is positive, the draw call is added to data relating to the previous render and the last shader is recompiled to replace an instruction that reads data from an identified buffer with an instruction that reads data from an on-chip register.
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公开(公告)号：US12106424B2
公开(公告)日：2024-10-01
申请号：US18244441
申请日：2023-09-11
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Steven J. Clohset , Ali Rabbani
Abstract: A ray tracing unit implemented in a graphics rendering system includes processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.
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