公开(公告)号：US20210109805A1

公开(公告)日：2021-04-15

申请号：US17129627

申请日：2020-12-21

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Qisong Lin ,  Shane Nowell ,  Mustafa N. Kaynak

IPC: G06F11/07 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14 ,  G06F3/06 ,  G11C16/34 ,  G11C29/00

Abstract: A determination that a programming operation has been performed on a memory cell can be made. An amount of time that has elapsed since the programming operation has been performed on the memory cell can be identified. A determination as to whether the amount of time that has elapsed satisfies a threshold time condition can be made. In response to determining that the amount of time that has elapsed satisfies the threshold time condition an operation can be performed on the memory cell to change or maintain a voltage condition of the memory cell.

公开(公告)号：US10977173B2

公开(公告)日：2021-04-13

申请号：US16167345

申请日：2018-10-22

Applicant: Micron Technology, Inc.

Inventor： Yun Li ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0891

Abstract: A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.

公开(公告)号：US10861573B2

公开(公告)日：2020-12-08

申请号：US16591686

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Aswin Thiruvengadam ,  Daniel L. Lowrance ,  Peter Feeley

IPC: G11C29/00 ,  G11C29/02 ,  G06F12/02 ,  G11C16/10 ,  G11C29/44

Abstract: Apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.

公开(公告)号：US10762003B2

公开(公告)日：2020-09-01

申请号：US16118501

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Victor Y. Tsai ,  James Cooke ,  Neal A. Galbo ,  Peter Feeley

IPC: G06F13/16 ,  G06F13/10 ,  G06F13/38 ,  G11C7/10 ,  G11C7/22 ,  G06F3/06 ,  G06F13/42

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

公开(公告)号：US20200210331A1

公开(公告)日：2020-07-02

申请号：US16237250

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Kulachet Tanpairoj ,  Peter Feeley ,  Sampath K. Ratnam ,  Ashutosh Malshe

IPC: G06F12/02 ,  G06F3/06

Abstract: A request to add content to a system data structure can be received. A first set of blocks of a common pool of blocks are allocated to the system data structure and a second set of blocks of the common pool of blocks are allocated to user data. A determination can be made as to whether a garbage collection operation associated with the first set of blocks of the common pool allocated to the system data structure satisfies a garbage collection performance condition. Responsive to determining that the garbage collection operation satisfies the garbage collection performance condition, a block from the common pool can be allocated to the first set of blocks allocated to the system data structure.

公开(公告)号：US10509722B2

公开(公告)日：2019-12-17

申请号：US15693178

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0891 ,  G06F3/06 ,  G06F12/06 ,  G11C11/56

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and designate a storage mode for an available memory block based on the valid data measure, wherein the storage mode is for controlling a number of bits stored per each of the memory cells for subsequent or upcoming data writes.

公开(公告)号：US20190139618A1

公开(公告)日：2019-05-09

申请号：US15802521

申请日：2017-11-03

Applicant: Micron Technology, Inc.

Inventor： Aswin Thiruvengadam ,  Daniel L. Lowrance ,  Peter Feeley

IPC: G11C29/02 ,  G11C16/10 ,  G06F12/02 ,  G11C16/32 ,  G06F3/06 ,  G06F17/30 ,  G11C7/10

CPC classification number: G11C29/028 ,  G06F3/0652 ,  G06F12/0246 ,  G06F12/0292 ,  G06F16/1847 ,  G06F2212/7209 ,  G11C7/04 ,  G11C7/1072 ,  G11C16/10 ,  G11C16/32 ,  G11C16/3495 ,  G11C2029/4402

Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.

公开(公告)号：US20190065365A1

公开(公告)日：2019-02-28

申请号：US15693153

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Yun Li ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam

IPC: G06F12/02 ,  G06F12/0891

Abstract: A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.

公开(公告)号：US10007465B2

公开(公告)日：2018-06-26

申请号：US14826583

申请日：2015-08-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Lance Dover ,  Jim Cooke ,  Peter Feeley

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06F12/06 ,  G06F12/02 ,  G06F13/12

CPC classification number: G06F3/065 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/1076 ,  G06F12/0223 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1673 ,  G06F2212/7205 ,  G06F2212/7207

Abstract: Methods of operating a memory device, and memory devices and systems so configured, include receiving a first address range for programming user data to a first range of physical memory addresses of a memory device, receiving a second address range for programming associated metadata to a second range of physical memory addresses of the memory device, determining whether the first address range is contiguous with the second address range, maintaining the second range of physical memory addresses for programming the metadata when it is determined that the second address range is contiguous with the first address range, and, when it is determined that the second address range is not contiguous with the first address range, remapping the second address range to a third range of physical memory addresses of the memory contiguous with the first range of physical memory addresses for programming the metadata.

公开(公告)号：US20180081543A1

公开(公告)日：2018-03-22

申请号：US15269518

申请日：2016-09-19

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F12/0893

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/7205 ,  G06F2212/7206

Abstract: A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including XLC blocks and a static cache including the SLC blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. A method of operating a memory device includes partitioning a memory array into a first portion of SLC blocks and a second portion of XLC blocks, storing at least a portion of host data into the first portion of SLC blocks as a static cache; and storing at least another portion of the host data into the second portion of XLC blocks in an SLC mode as a dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. Additional memory devices, methods, and computer systems are also described.