公开(公告)号：US20230044047A1

公开(公告)日：2023-02-09

申请号：US17959557

申请日：2022-10-04

Applicant: Tokyo Electron Limited

Inventor： Junling Sun ,  Lior Huli ,  Andrew Metz ,  Angelique Raley

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311

Abstract: Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

公开(公告)号：US20220181152A1

公开(公告)日：2022-06-09

申请号：US17116911

申请日：2020-12-09

Applicant: Tokyo Electron Limited

Inventor： Junling Sun ,  Katie Lutker-Lee ,  Angelique Raley ,  Andrew Metz

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/66 ,  H01L21/768

Abstract: A method for forming a device includes forming a hole pattern in a resist layer disposed over a substrate. The substrate includes contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions. The resist layer is disposed over the dielectric layer and the hole pattern includes through openings in the resist layer that are aligned with the contact regions. The through openings include a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension. The method includes modifying the hole pattern by depositing a material including silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture including SiCl4 and hydrogen, and then etching holes in the dielectric layer through the modified hole pattern, exposing the contact regions.

公开(公告)号：US20220076942A1

公开(公告)日：2022-03-10

申请号：US17014515

申请日：2020-09-08

Applicant: Tokyo Electron Limited

Inventor： Katie Lutker-Lee ,  David O'Meara ,  Angelique Raley

IPC: H01L21/027 ,  H01L21/02 ,  H01L21/311

Abstract: Improved process flows and methods are provided herein for trimming structures formed on a patterned substrate. In the disclosed process flows and methods, a self-aligned multiple patterning (SAMP) process is utilized for patterning structures, such as mandrels, on a substrate. After the structures are patterned, an atomic layer deposition (ALD) process is used to form a spacer layer on the patterned structures. In the SAMP process disclosed herein, a critical dimension (CD) of the patterned structures is trimmed concurrently with, and as a result of, the formation of the spacer layer by controlling various ALD process parameters and conditions. By trimming the patterned structures in situ of the ALD chamber used to form the spacer layer on the patterned structures, the improved process flows and methods described herein provide a CD trim method that does not adversely affect the pattern profile or process throughput.

公开(公告)号：US11227767B2

公开(公告)日：2022-01-18

申请号：US16401527

申请日：2019-05-02

Applicant: Tokyo Electron Limited

Inventor： Angelique Raley ,  Kal Subhadeep

IPC: H01L21/033 ,  H01L21/311

Abstract: A substrate is provided with a patterned layer over a stack of one or more processing layers. The processing layers include at least one patterned layer and one etch target layer. CD trimming between the CD of the patterned layer and the CD of the etch target layer may be achieved after the pattern is transferred to the etch target layer. After the etch target layer is patterned, a plasma free gas phase etch process may be used to trim the CD of the etch target layer to finely tune the CD. In an alternate embodiment, plasma etch trim processes may be used in combination with the gas phase etch process. In such an embodiment, partial CD trimming may be achieved via the plasma etching of the various process layers and then additional CD trimming may be achieved by subjecting the etch target layer to the plasma free gas phase etch after the desired pattern has been formed in the etch target layer.

公开(公告)号：US11164781B2

公开(公告)日：2021-11-02

申请号：US16508923

申请日：2019-07-11

Applicant: Tokyo Electron Limited

Inventor： Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  David O'Meara ,  Jeffrey Smith

IPC: H01L21/768 ,  H01L21/02

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

公开(公告)号：US11127594B2

公开(公告)日：2021-09-21

申请号：US16211520

申请日：2018-12-06

Applicant: Tokyo Electron Limited

Inventor： Xinghua Sun ,  Angelique Raley ,  Andrew Metz

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213

Abstract: Embodiments are disclosed for processing microelectronic workpieces having patterned structures to improve mandrel pull from spacers for multi-color patterning. The disclosed embodiments form patterned structures on a substrate including mandrels, form spacers adjacent the mandrels that are recessed such that a height of the spacers is less than the height of the mandrels, form protective caps over the spacers while exposing top surfaces of the mandrels, and remove the mandrels to leave a spacer pattern with cap protection. The remaining spacer pattern can then be transferred to underlying layers in additional process steps. The recessing of the spacers and formation of the protective caps tends to reduce or eliminate spacer damage suffered by prior solutions during mandrel pull from spacers for multi-color patterning.

公开(公告)号：US11101173B2

公开(公告)日：2021-08-24

申请号：US16356372

申请日：2019-03-18

Applicant: Tokyo Electron Limited

Inventor： Robert Clark ,  Jeffrey Smith ,  Kandabara Tapily ,  Angelique Raley ,  Qiang Zhao

IPC: H01L21/67 ,  H01L21/768 ,  H01L21/66 ,  H01L21/677 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418 ,  C23C14/24 ,  C23C14/34 ,  H01J37/32

Abstract: This disclosure relates to a method for using a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The system includes an active interdiction control system to implement corrective processing within the system when a non-conformity is detected. The corrective processing method can include a remedial process sequence to correct the non-conformity or compensate for the non-conformity during subsequent process. The non-conformity may be associated with fabrication measurement data, process parameter data, and/or platform performance data.

公开(公告)号：US10950460B2

公开(公告)日：2021-03-16

申请号：US16533354

申请日：2019-08-06

Applicant: Tokyo Electron Limited

Inventor： Angelique Raley ,  Andrew Metz ,  Cory Wajda ,  Junling Sun

IPC: H01L21/3213 ,  H01L21/56 ,  H01L21/311 ,  H01L21/02

Abstract: A process is provided in which etched layer(s) are protected from residues or defects caused by or resulting from exposure to atmospheric conditions. Protection is provided through the formation of an encapsulation layer post etch. In one embodiment, the encapsulation is provided by a thin layer formed in an atomic layer deposition (ALD) process. The thin layer prevents the etched layer(s) from exposure to air. This encapsulation process may take place after the etch process thus allowing for substrates to be subsequently exposed to atmospheric conditions with little or no queue time constraints being needed for staging subsequent wet clean processing steps. In one embodiment, the encapsulation process may be performed with no vacuum break between the etch process and the encapsulation process. In one embodiment, the encapsulation film is compatible with subsequent wet process steps and can be removed during this wet process steps without adverse effects.

公开(公告)号：US20210028017A1

公开(公告)日：2021-01-28

申请号：US16582297

申请日：2019-09-25

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Angelique Raley

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311

Abstract: A method of processing substrates, in one example microelectronic workpieces, is disclosed that includes forming a multi-layer metal hard mask (MHM) layer in which at least one lower layer of the multi-layer MHM is comprised of ruthenium (Ru). The Ru MHM layer may be an atomic layer deposition (ALD) Ru MHM layer formed over one or more underlying layers on a substrate. The ALD Ru MHM layer may be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers may be etched using, at least in part, the patterned ALD Ru MHM layer as a mask to protect portion of the one or more underlying layers. In one embodiment, at least one of the underlying layers is a hard mask layer.

公开(公告)号：US20200043764A1

公开(公告)日：2020-02-06

申请号：US16356334

申请日：2019-03-18

Applicant: Tokyo Electron Limited

Inventor： Robert Clark ,  Eric Chih-Fang Liu ,  Angelique Raley ,  Holger Tuitje ,  Kevin Siefering

IPC: H01L21/67 ,  H01L21/687 ,  G05B19/418

Abstract: This disclosure relates to a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The systems process chambers are connected to each other via transfer chambers used to move the workpieces, in the controlled environment, between the process chambers. The transfer chambers include a measurement region with dedicated workpiece support chucks capable of translating and/or rotating the workpiece during the measurement.