公开(公告)号：US11756790B2

公开(公告)日：2023-09-12

申请号：US17196385

申请日：2021-03-09

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Xinghua Sun ,  Shihsheng Chang ,  Eric Chih-Fang Liu ,  Angelique Raley ,  Katie Lutker-Lee

IPC: H01L21/033 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/0332 ,  H01L21/3065 ,  H01L21/3081

Abstract: A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.

公开(公告)号：US20210265205A1

公开(公告)日：2021-08-26

申请号：US17179117

申请日：2021-02-18

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Xinghua Sun ,  Michael Edley ,  Angelique Raley

IPC: H01L21/768

Abstract: Stacked structures, process steps, and methods for via and trench formation use a dielectric etch stop layer (ESL) to reduce or eliminate problems, such as process lag and chamfer erosion, that occur during conventional etch processes. A stacked structure is formed that includes a dielectric ESL within a dielectric layer, such as a low-dielectric (low-K) layer, to form a first low-K layer below the dielectric ESL and a second low-K dielectric layer above the dielectric ESL. When the stacked structure is subsequently etched to form trenches as well as vias through the stacked structure to underlying layers, the dielectric ESL reduces or eliminates RIE lag by ensuring that trenches (regardless of width) stop on the dielectric ESL. The dielectric ESL also acts as a protective layer to protect corners from chamfer erosion during via and trench etch processes.

公开(公告)号：US10964587B2

公开(公告)日：2021-03-30

申请号：US16415687

申请日：2019-05-17

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  David O'Meara ,  Angelique Raley ,  Xinghua Sun

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/308

Abstract: An atomic layer deposition (ALD) technique is used to deposit one or more layers on hard mask layers and the sidewalls of low-K dielectric trench as part of the trench etch process. The ALD layer(s) can prevent the hard mask from being eroded during various hard mask open processes. Further, the ALD layer(s) may be utilized to prevent the low-K dielectric sidewall from being laterally etched during the low-K dielectric trench etch. Hence, better control of the trench profile and better critical dimension control may be provided.

公开(公告)号：US11742241B2

公开(公告)日：2023-08-29

申请号：US17487987

申请日：2021-09-28

Applicant: TOKYO ELECTRON LIMITED

Inventor： Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  David O'Meara ,  Jeffrey Smith

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027 ,  H01L21/3205

CPC classification number: H01L21/76897 ,  H01L21/0228 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/32056 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

公开(公告)号：US20190355617A1

公开(公告)日：2019-11-21

申请号：US16415687

申请日：2019-05-17

Applicant: Tokyo Electron Limited

Inventor： David O'Meara ,  Angelique Raley ,  Xinghua Sun ,  Yen-Tien Lu

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/762

Abstract: An atomic layer deposition (ALD) technique is used to deposit one or more layers on hard mask layers and the sidewalls of low-K dielectric trench as part of the trench etch process. The ALD layer(s) can prevent the hard mask from being eroded during various hard mask open processes. Further, the ALD layer(s) may be utilized to prevent the low-K dielectric sidewall from being laterally etched during the low-K dielectric trench etch. Hence, better control of the trench profile and better critical dimension control may be provided.

公开(公告)号：US11532517B2

公开(公告)日：2022-12-20

申请号：US16781078

申请日：2020-02-04

Applicant: Tokyo Electron Limited

Inventor： Yun Han ,  Andrew Metz ,  Xinghua Sun ,  David L. O'Meara ,  Kandabara Tapily ,  Henan Zhang ,  Shan Hu

IPC: H01L21/8234 ,  H01L21/20 ,  H01L21/311 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: In one embodiment, a method includes providing a substrate comprising a source/drain contact region and a dummy gate, forming a first etch stop layer aligned to the source/drain contact region, where the first etch stop layer does not cover the dummy gate. The method may include forming a second etch stop layer over the first etch stop layer, the second etch stop layer covering the first etch stop layer and the dummy gate. The method may include converting the dummy gate to a metal gate. The method may include removing the second etch stop layer using a plasma etching process. The method may include removing the first etch stop layer.

公开(公告)号：US11515203B2

公开(公告)日：2022-11-29

申请号：US16782344

申请日：2020-02-05

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Xinghua Sun ,  Angelique Raley

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67 ,  H01L21/311

Abstract: Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

公开(公告)号：US11121027B2

公开(公告)日：2021-09-14

申请号：US16213628

申请日：2018-12-07

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Xinghua Sun ,  Eric Chih-Fang Liu ,  Andrew W. Metz

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

Abstract: A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.

公开(公告)号：US20200051859A1

公开(公告)日：2020-02-13

申请号：US16508923

申请日：2019-07-11

Applicant: Tokyo Electron Limited

Inventor： Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  David O'Meara ,  Jeffrey Smith

IPC: H01L21/768 ,  H01L21/02

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

公开(公告)号：US20190181041A1

公开(公告)日：2019-06-13

申请号：US16213628

申请日：2018-12-07

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Xinghua Sun ,  Eric Chih-Fang Liu ,  Andrew W. Metz

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

Abstract: A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.