公开(公告)号：US20170194349A1

公开(公告)日：2017-07-06

申请号：US15466871

申请日：2017-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Chun-Hsien Wu

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11885

Abstract: An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes one first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type. And an area of the first doped region is smaller than an area of the total second doped regions.

公开(公告)号：US20170098692A1

公开(公告)日：2017-04-06

申请号：US14936370

申请日：2015-11-09

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0615 ,  H01L21/2253 ,  H01L21/76802 ,  H01L21/76871 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US09331185B2

公开(公告)日：2016-05-03

申请号：US14505513

申请日：2014-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Huang ,  Shen-De Wang ,  Wen-Chung Chang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: H01L21/336 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/792

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

Abstract translation: 一种用于制造非易失性存储结构的方法包括提供具有栅极结构的衬底，执行第一氧化工艺以形成至少覆盖导电层的底角的第一SiO层，执行第一蚀刻工艺以除去第一 SiO层和所述电介质层的一部分以形成空腔，执行第二氧化工艺以形成覆盖所述空腔的侧壁的第二SiO层和覆盖所述衬底的表面的第三SiO层，形成填充在所述腔中的第一SiN层 并且覆盖衬底上的栅极结构，并且去除第一SiN层的一部分以形成SiN结构，其包括填充在空腔中的脚部和从脚部向上延伸的勃起部，以及覆盖侧壁的安装部 门结构。

公开(公告)号：US09331184B2

公开(公告)日：2016-05-03

申请号：US13914641

申请日：2013-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Sheng Yang ,  Chien-Hung Chen

IPC: H01L29/66 ,  H01L29/792 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.

Abstract translation: 公开了一种氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）器件。 SONOS器件包括衬底; 衬底上的第一氧化物层; 在所述第一氧化物层上的富硅捕获层; 富硅捕获层上的含氮层; 含氮层上的富硅氧化物层; 和富硅氧化物层上的多晶硅层。

公开(公告)号：US09323883B2

公开(公告)日：2016-04-26

申请号：US14337187

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Yao Chiang ,  Kuo-Hsun Huang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068

Abstract: A planar design to non-planar design conversion method includes following steps. At least a diffusion region pattern including a first side and a second side perpendicular to each other is received. A look-up table is queried to obtain a first positive integer according to the first side of the diffusion region pattern and a second positive integer according to the second side of the diffusion region pattern. Then, a plurality of fin patterns is formed. An amount of the fin patterns is equal to the second positive integer. The fin patterns respectively include a first fin length, and the first fin length is a product of the first positive integer and a predetermined value. The forming is performed by at least a computer-aided design (CAD) tool.

Abstract translation: 非平面设计转换方法的平面设计包括以下步骤。 至少包括彼此垂直的第一侧和第二侧的扩散区图案。 查询表根据扩散区域图案的第一侧获得第一正整数，并根据扩散区图案的第二侧获得第二正整数。 然后，形成多个翅片图案。 鳍图案的数量等于第二正整数。 翅片图案分别包括第一翅片长度，并且第一翅片长度是第一正整数和预定值的乘积。 至少由计算机辅助设计（CAD）工具进行成型。

公开(公告)号：US20160004806A1

公开(公告)日：2016-01-07

申请号：US14324231

申请日：2014-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsun Huang ,  Hsi-Chang Chang ,  Chao-Yao Chiang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/504 ,  G06F17/5081

Abstract: A computer implemented method for performing extraction is provided in the present invention. First, a layout of a semiconductor circuit having a resistor is imported by using a computer wherein a device region is defined in the layout and the resistor is located within the device region. Next, the device region of the layout are extracted, and a compensation value of Rs (Rc) is obtained according to the extracting step. An adjustment process is performed according to Rc to obtained a refined R value.

Abstract translation: 本发明提供了一种用于执行提取的计算机实现方法。 首先，通过使用其中在布局中限定器件区域并且电阻器位于器件区域内的计算机来导入具有电阻器的半导体电路的布局。 接下来，提取布局的设备区域，并且根据提取步骤获得Rs（Rc）的补偿值。 根据Rc执行调整处理以获得精确的R值。

公开(公告)号：US20150008504A1

公开(公告)日：2015-01-08

申请号：US13935570

申请日：2013-07-05

Applicant: United Microelectronics Corp.

Inventor： Chun-Lung Chang ,  Tzu-Ping Chen ,  Chih-Haw Lee ,  Kuan-Yi Tseng ,  Chih-Jung Chen ,  Chien-Hung Chen

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/66833 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/7923

Abstract: A non-volatile memory structure includes a substrate, a gate electrode formed on the substrate, conductive spacers respectively formed on two sides of the gate electrode, and an oxide-nitride-oxide (ONO) structure having an inverted T shape formed on the substrate. The gate electrode includes a gate conductive layer and a gate dielectric layer. The ONO structure includes a base portion and a body portion. The base portion of the ONO structure is sandwiched between the gate electrode and the substrate, and between the conductive spacer and the substrate. The body portion of the T-shaped ONO structure is upwardly extended from the base portion and sandwiched between the gate electrode and the conductive spacer.

Abstract translation: 非易失性存储器结构包括：衬底，形成在衬底上的栅极电极，分别形成在栅电极的两侧上的导电衬垫和在衬底上形成有倒T形的氧化物 - 氧化物（ONO）结构 。 栅电极包括栅极导电层和栅极电介质层。 ONO结构包括基部和主体部分。 ONO结构的基部被夹在栅电极和衬底之间以及导电间隔物和衬底之间。 T形ONO结构的主体部分从基部向上延伸并夹在栅电极和导电间隔件之间。

公开(公告)号：US20140198574A1

公开(公告)日：2014-07-17

申请号：US13741442

申请日：2013-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shen-De Wang ,  Wen-Chung Chang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: G11C16/14 ,  G11C16/10 ,  H01L27/088

CPC classification number: G11C16/14 ,  G11C16/0475 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/088 ,  H01L27/11565 ,  H01L27/11568

Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.

Abstract translation: 提供了一种非易失性存储器的操作方法，包括以下步骤。 提供具有多个存储单元的非易失性存储器。 两个相邻的存储器单元对应于一个位，并且包括基板，第一和第二第一掺杂区域，第二掺杂区域，电荷俘获层，控制栅极，第一位线，源极线和与 第一个位线。 形成第一和第二通道。 电荷捕获层设置在第一和第二通道上。 通过以下步骤对相邻的两个存储单元进行编程。 第一正电压和负电压分别施加到第一和第二掺杂区域之间的控制栅极以及第二和第二掺杂区域之间的控制栅极。 第一个电压被施加到源极线。

公开(公告)号：US20140092689A1

公开(公告)日：2014-04-03

申请号：US13633732

申请日：2012-10-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Feng-Ji Tsai ,  Shen-De Wang ,  Wen-Chung Chang ,  Ya-Huei Huang ,  Chien-Hung Chen

IPC: G11C16/10 ,  H01L29/792 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/26 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/7923

Abstract: A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated secondary electron (CHISEL) injection process to inject electrons to the charge-trapping structure.

Abstract translation: 描述用于编程非易失性存储器单元的方法。 存储单元包括衬底，衬底上的栅极，至少在衬底和栅极之间的电荷捕获结构以及栅极旁边的衬底中的第一和第二S / D区域。 该方法包括执行通道引发的二次电子（CHISEL）注入过程以将电子注入电荷捕获结构。