公开(公告)号：US20160380081A1

公开(公告)日：2016-12-29

申请号：US14818322

申请日：2015-08-05

Applicant: United Microelectronics Corp.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A FinFET includes a substrate. Numerous fin structures are defined on the substrate. A gate structure crosses each fin structure. Two epitaxial layers are disposed at two side of the gate structure, respectively. Each epitaxial layer has a top surface including a second recessed and protruding profile. A contact plug contacts the second recessed and protruding profile. The second recessed and protruding profile increases the contact area between the contact plug and the epitaxial layer.

Abstract translation: FinFET包括衬底。 在衬底上限定了许多翅片结构。 栅极结构跨越每个鳍结构。 两个外延层分别设置在栅极结构的两侧。 每个外延层具有包括第二凹入和突出轮廓的顶表面。 接触插头接触第二凹入和突出的轮廓。 第二凹入和突出的轮廓增加了接触插塞和外延层之间的接触面积。

公开(公告)号：US20160358827A1

公开(公告)日：2016-12-08

申请号：US15241077

申请日：2016-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/84 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/845 ,  H01L21/02238 ,  H01L21/02365 ,  H01L21/02367 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/7624 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-shaped structure includes the following step. A substrate having a first area and a second area is provided. An epitaxial structure is formed in the first area. An epitaxial structure is formed in the second area after the epitaxial structure in the first area is formed, wherein the surface area of the epitaxial structure in the first area is different from the surface area of the epitaxial structure in the second area.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 提供具有第一区域和第二区域的衬底。 在第一区域中形成外延结构。 在形成第一区域中的外延结构之后，在第二区域中形成外延结构，其中第一区域中的外延结构的表面积与第二区域中的外延结构的表面积不同。

公开(公告)号：US09443954B2

公开(公告)日：2016-09-13

申请号：US15009808

申请日：2016-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966

Abstract: The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a first semiconductor device and a second semiconductor device are formed on the substrate, having a first gate trench and a second trench respectively. Next, a bottom barrier layer is formed in the first gate trench and a second trench. Afterwards, a first pull back step is performed, to remove parts of the bottom barrier layer, and a first work function metal layer is then formed in the first gate trench. Next, a second pull back step is performed, to remove parts of the first work function metal layer, wherein the topmost portion of the first work function metal layer is lower than the openings of the first gate trench and the second gate trench.

Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 该方法首先包括衬底，并且在衬底上形成第一半导体器件和第二半导体器件，分别具有第一栅极沟槽和第二沟槽。 接下来，在第一栅极沟槽和第二沟槽中形成底部阻挡层。 之后，执行第一回拉步骤以去除底部阻挡层的部分，然后在第一栅极沟槽中形成第一功函数金属层。 接下来，执行第二拉回步骤以去除第一功函数金属层的部分，其中第一功函数金属层的最顶部比第一栅沟槽和第二栅沟的开口低。

公开(公告)号：US09349833B1

公开(公告)日：2016-05-24

申请号：US14614416

申请日：2015-02-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chao-Hung Lin ,  Ying-Tsung Chen ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Shih-Hung Tsai

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are disposed on a substrate, and each gate structure includes a gate electrode, a capping layer and a spacer surrounding the gate electrode and the capping layer. The source/drain region is disposed at two sides of the gate electrode. The first dielectric layer is disposed on the substrate and has a height being less than a height of the gate electrode. The floating spacer is disposed on a side wall of the spacer, and also on the first dielectric layer.

Abstract translation: 半导体器件包括多个栅极结构，源极/漏极区，第一电介质层和浮置间隔物。 栅极结构设置在衬底上，并且每个栅极结构包括栅电极，覆盖层和围绕栅电极和覆盖层的间隔物。 源极/漏极区域设置在栅电极的两侧。 第一介电层设置在基板上，其高度小于栅电极的高度。 浮动间隔件设置在间隔件的侧壁上，也位于第一介电层上。

公开(公告)号：US20240395909A1

公开(公告)日：2024-11-28

申请号：US18791454

申请日：2024-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

公开(公告)号：US20240213247A1

公开(公告)日：2024-06-27

申请号：US18107983

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Lin ,  Zen-Jay Tsai ,  Chun-Hsien Lin

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method for fabricating a semiconductor device includes providing a substrate having a first region and a second region, forming a first gate dielectric layer on the first region, forming a second gate dielectric layer on the second region, and forming a first gate structure on the first gate dielectric layer and the second gate dielectric layer. Preferably, the first gate dielectric layer and the second gate dielectric layer have different thicknesses.

公开(公告)号：US11990507B2

公开(公告)日：2024-05-21

申请号：US17403578

申请日：2021-08-16

Applicant: United Microelectronics Corp.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/1095 ,  H01L29/7816

Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.

公开(公告)号：US11948975B2

公开(公告)日：2024-04-02

申请号：US17509061

申请日：2021-10-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/665

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

公开(公告)号：US11901239B2

公开(公告)日：2024-02-13

申请号：US18104307

申请日：2023-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

公开(公告)号：US20230268346A1

公开(公告)日：2023-08-24

申请号：US17700475

申请日：2022-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chin-Hung Chen

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.